MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 90
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MCF5307CFT66B
Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307CFT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
FREESCAL
Quantity:
154
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Exception Processing Overview
2.8.2 Processor Exceptions
Table 2-21 describes MCF5307 exceptions.
2-50
Access Error
Address
Error
Illegal
Instruction
Divide by
Zero
Privilege
Violation
Exception
• Vector number—This 8-bit field, vector[7–0], defines the exception type. It is
calculated by the processor for internal faults and is supplied by the peripheral for
interrupts. See Table 2-18.
0101–011x
1101–111x
0001-001x
FS[3–0]
Access errors are reported only in conjunction with an attempted store to write-protected memory.
Thus, access errors associated with instruction fetch or operand read accesses are not possible.
Caused by an attempted execution transferring control to an odd instruction address (that is, if bit 0 of
the target address is set), an attempted use of a word-sized index register (Xi.w) or a scale factor of
8 on an indexed effective addressing mode, or attempted execution of an instruction with a full-format
indexed addressing mode.
On Version 2 ColdFire implementations, only some illegal opcodes were decoded and generated an
illegal instruction exception. The Version 3 processor decodes the full 16-bit opcode and generates
this exception if execution of an unsupported instruction is attempted. Additionally, attempting to
execute an illegal line A or line F opcode generates unique exception types: vectors 10 and 11,
respectively.
ColdFire processors do not provide illegal instruction detection on extension words of any instruction,
including MOVEC. Attempting to execute an instruction with an illegal extension word causes
undefined results.
Attempted division by zero causes an exception (vector 5, offset = 0x014) except when the PC points
to the faulting instruction (DIVU, DIVS, REMU, REMS).
Caused by attempted execution of a supervisor mode instruction while in user mode. The ColdFire
Programmer’s Reference Manual lists supervisor- and user-mode instructions.
0000
0100
1000
1001
1100
101x
Not an access or address error
Reserved
Error on instruction fetch
Reserved
Error on operand write
Attempted write to write-protected space
Reserved
Error on operand read
Reserved
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 2-20. Fault Status Encodings
Table 2-21. MCF5307 Exceptions
Go to: www.freescale.com
MCF5307 User’s Manual
Description
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