MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 367

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Address
Data
Read/Write
Size
Transfer start
Address strobe
Transfer acknowledge
Transfer in progress
Transfer type
Transfer modifier
Interrupt request
Bus request
Bus grant
Bus driven
Reset in
Clock input
Bus clock out
Reset out
Auto-acknowledge
configuration
Port size configuration
Address configuration
Signal Name
2
2
2
A[31:0]
D[31:0]
R/W
SIZ[1:0]
TS
AS
TA
TIP/PP7
TT[1:0]
TM[2:0]
IRQ7, IRQ5,
IRQ3, IRQ1
BR
BG
BD
RSTI
CLKIN
BCLKO
RSTO
AA_CONFIG
PS_CONFIG[1:0] Controls port size for CS0 at reset
ADDR_CONFIG
Abbreviation
Freescale Semiconductor, Inc.
Section 17.3, “Interrupt Control Signals”
For More Information On This Product,
Section 17.5, “Clock and Reset Signals”
Table 17-1. MCF5307 Signal Index
Section 17.4, “Bus Arbitration Signals”
Section 17.2, “MCF5307 Bus Signals”
Chapter 17. Signal Descriptions
Go to: www.freescale.com
32-bit address bus. A[4:2] indicate
the interrupt level for external
interrupts.
Data bus. D[7:0] are loaded at reset
for bus configuration.
Identifies read and write transfers
Indicates the data transfer size
Indicates the start of a bus transfer
Indicates a bus cycle has been
initiated and address is stable
Assertion terminates transfer
synchronously
Indicates a bus cycle is in progress;
multiplexed with PP7
Indicates transfer type: normal, CPU
space, emulator mode, or DMA;
multiplexed with PP[1:0]
Provides transfer modifier
information; Multiplexed with
PP[4:2].
Four external interrupts are set to
default levels 1,3,5,7; user-alterable.
Indicates processor needs bus
Arbiter asserts to grant mastership.
Indicates processor is driving bus
Processor reset input
Input used to clock internal logic
Bus clock reference output
Processor reset output
Controls auto acknowledge timing
for CS0 at reset
Programs parallel I/O ports
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Parallel
Parallel
Parallel
Reset
Three
Three
Three
Three
Three
Three
Three
state
state
state
state
state
state
state
High
High
port
port
port
Low
—
—
—
—
—
—
—
—
User cfg 17-14
User cfg 17-14
Pull-Up Page
Note
Up
Up
Up
Up
Up
Overview
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17-7
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17-3