MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 119
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MCF5307CFT66B
Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307CFT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
FREESCAL
Quantity:
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Part Number:
MCF5307CFT66B
Manufacturer:
Freescale Semiconductor
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4.10 Cache Registers
This section describes the MCF5307 implementation of the Version 3 cache registers.
4.10.1 Cache Control Register (CACR)
The CACR in Figure 4-8 contains bits for configuring the cache. It can be written by the
MOVEC register instruction and can be read or written from the debug facility. A hardware
reset clears CACR, which disables the cache; however, reset does not affect the tags, state
information, or data in the cache.
Table 4-4 describes CACR fields.
31
30
29
28
Bits
Reset
Reset
Field EC
Field
R/W
R/W
Rc
—
ESB
Name
31
15
DPI
EC
—
30
14
Enable cache.
0 Cache disabled. The cache is not operational, but data and tags are preserved.
1 Cache enabled.
Reserved, should be cleared.
Enable store buffer.
0 Writes to write-through or noncachable in imprecise mode bypass the store buffer and
1 The four-entry FIFO store buffer is enabled; when imprecise mode is used, this buffer defers
Cache-inhibited, precise-mode accesses always bypass the store buffer.
Disable CPUSHL invalidation.
0 Normal operation. A CPUSHL instruction causes the selected line to be pushed if modified and
1 No clear operation. A CPUSHL instruction causes the selected line to be pushed if modified,
ESB
generate bus cycles directly. Section 4.9.5.2.1, “Push and Store Buffers,” describes the
performance penalty for this.
pending writes to write-through or cache-inhibited regions to maximize performance.
then invalidated.
then left valid.
29
13
—
Figure 4-8. Cache Control Register (CACR)
DPI
28
12
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-4. CACR Field Descriptions
HLCK
27
11
Chapter 4. Local Memory
Go to: www.freescale.com
DNFB
26
10
Write (R/W by debug module)
Write (R/W by debug module)
—
0000_0000_0000_0000
0000_0000_0000_0000
25
9
DCM
CINVA
0x002
24
8
Description
23
7
—
DW
20
—
19
Cache Registers
—
18
17
4-21
16
0
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