MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 250

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Freescale Semiconductor, Inc.
Synchronous Operation
11.3.3.5 Refresh Operation
The DRAM controller supports CAS-before-RAS refresh operations that are not
synchronized to bus activity. A special DRAMW pin is provided so refresh can occur
regardless of the state of the processor bus.
When the refresh counter rolls over, it sets an internal flag to indicate that a refresh is
pending. If that happens during a continuous page-mode access, the page is closed (RAS
precharged) when the data transfer completes to allow the refresh to occur. The flag is
cleared when the refresh cycle is run. Both memory blocks are simultaneously refreshed as
determined by the DCR. DRAM accesses are delayed during refresh. Only an active bus
access to a DRAM block can delay refresh.
Figure 11-12 shows a bus cycle delayed by a refresh operation. Notice that DRAMW is
forced high during refresh. The row address is held until the pending DRAM access.
BCLKO
A[31:0]
RRP = 01
RAS[1] or [0]
RRA = 01
CAS[3:0]
DRAMW
Refresh
Access
Figure 11-12. DRAM Access Delayed by Refresh
11.4 Synchronous Operation
By running synchronously with the system clock instead of responding to asynchronous
control signals, SDRAM can (after an initial latency period) be accessed on every clock;
5-1-1-1 is a typical MCF5307 burst rate to SDRAM.
Note that because the MCF5307 cannot have more than one page open at a time, it does not
support interleaving.
SDRAM controllers are more sophisticated than asynchronous DRAM controllers. Not
only must they manage addresses and data, but they must send special commands for such
functions as precharge, read, write, burst, auto-refresh, and various combinations of these
functions. Table 11-10 lists common SDRAM commands.
11-16
MCF5307 User’s Manual
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