MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 38

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Terminology and Notational Conventions
xxxviii
sign-extended
If <condition>
<operations>
<operations>
Instruction
# <vector>
Address
<xxx>
MSW
LSW
MSB
←→
then
LSB
msb
else
SF
lsb
dn
<<
>>
Bit
→
d
ic
&
{}
()
+
–
x
~
^
/
|
n
identifies an indirect data address referencing memory
Instruction cache
Identifies the 4-bit vector number for trap instructions
identifies an absolute address referencing memory
Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)
Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)
Arithmetic addition or postincrement indicator
Arithmetic subtraction or predecrement indicator
Arithmetic multiplication
Arithmetic division
Invert; operand is logically complemented
Logical AND
Logical OR
Logical exclusive OR
Shift left (example: D0 << 3 is shift D0 left 3 bits)
Shift right (example: D0 >> 3 is shift D0 right 3 bits)
Source operand is moved to destination operand
Two operands are exchanged
All bits of the upper portion are made equal to the high-order bit of the lower portion
Test the condition. If true, the operations after ‘then’ are performed. If the condition is false and the
optional ‘else’ clause is present, the operations after ‘else’ are performed. If the condition is false
and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description
as an example.
Optional operation
Identifies an indirect address
Displacement value, n-bits wide (example: d
Calculated effective address (pointer)
Bit selection (example: Bit 3 of D0)
Least significant bit (example: lsb of D0)
Least significant byte
Least significant word
Most significant bit
Most significant byte
Most significant word
Table ii Notational Conventions (Continued)
Freescale Semiconductor, Inc.
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MCF5307 User’s Manual
Subfields and Qualifiers
Operations
Operand Syntax
16
is a 16-bit displacement)