MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 136

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Programming Model
5.4.2 Address Breakpoint Registers (ABLR, ABHR)
The address breakpoint low and high registers (ABLR, ABHR), Figure 5-6, define regions
in the processor’s data address space that can be used as part of the trigger. These register
values are compared with the address for each transfer on the processor’s high-speed local
bus. The trigger definition register (TDR) identifies the trigger as one of three cases:
5-8
15
14–13 SZM
12–11 TTM
10–8
7
6–5
4–3
2–0
Bits
1. identically the value in ABLR
2. inside the range bound by ABLR and ABHR inclusive
3. outside that same range
Name
RM
TMM
R
SZ
TT
TM
Read/write mask. Setting RM masks R in address comparisons.
Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons.
Transfer type mask. Setting a TTM bit masks the corresponding TT bit in address comparisons.
Transfer modifier mask. Setting a TMM bit masks the corresponding TM bit in address comparisons.
Read/write. R is compared with the R/W signal of the processor’s local bus.
Size. Compared to the processor’s local bus size signals.
00 Longword
01 Byte
10 Word
11 Reserved
Transfer type. Compared with the local bus transfer type signals.
00 Normal processor access
01 Reserved
10 Emulator mode access
11 Acknowledge/CPU space access
These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding
indicates an external or DMA access (for backward compatibility). These bits affect the TM bits.
Transfer modifier. Compared with the local bus transfer modifier signals, which give supplemental
information for each transfer type.
TT = 00 (normal mode):
000 Explicit cache line push
001 User data access
010 User code access
011 Reserved
100 Reserved
101 Supervisor data access
110 Supervisor code access
111 Reserved
TT = 10 (emulator mode):
0xx–100 Reserved
101 Emulator mode data access
110 Emulator mode code access
111 Reserved
TT = 11 (acknowledge/CPU space transfers):
000 CPU space access
001–111 Interrupt acknowledge levels 1–7
These bits also define the TM encoding for BDM memory commands (for backward compatibility).
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5-4. AATR Field Descriptions
Go to: www.freescale.com
MCF5307 User’s Manual
Description