MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 87

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

if bcc is a forward branch && CCR[7] == 1
Table 2-17 shows timing for Bcc instructions.
2.8 Exception Processing Overview
Exception processing for ColdFire processors is streamlined for performance. Differences
from previous M68000 Family processors include the following:
ColdFire processors use an instruction restart exception model but require more software
support to recover from certain access errors. See Table 2-18 for details.
Exception processing can be defined as the time from the detection of the fault condition
until the fetch of the first handler instruction has been initiated. It is comprised of the
following four major steps:
• A simplified exception vector table
• Reduced relocation capabilities using the vector base register
• A single exception stack frame format
• Use of a single, self-aligning system stack pointer
1. The processor makes an internal copy of the SR and then enters supervisor mode by
2. The processor determines the exception vector number. For all faults except
3. The processor saves the current context by creating an exception stack frame on the
setting SR[S] and disabling trace mode by clearing SR[T]. The occurrence of an
interrupt exception also forces SR[M] to be cleared and the interrupt priority mask
to be set to the level of the current interrupt request.
interrupts, the processor performs this calculation based on the exception type. For
interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to
obtain the vector number from a peripheral device. The IACK cycle is mapped to a
special acknowledge address space with the interrupt level encoded in the address.
system stack. ColdFire processors support a single stack pointer in the A7 address
register; therefore, there is no notion of separate supervisor and user stack pointers.
As a result, the exception stack frame is created at a 0-modulo-4 address on the top
of the current system stack. Additionally, the processor uses a simplified
then the bcc is predicted as taken
else if bcc is a backward branch
then the bcc is predicted as taken
Opcode
Table 2-17. Bcc Instruction Execution Times
bcc
Freescale Semiconductor, Inc.
For More Information On This Product,
Correctly as Taken
Predicted
1(0/0)
Chapter 2. ColdFire Core
Go to: www.freescale.com
Correctly as Not
Predicted
Taken
1(0/0)
Exception Processing Overview
Incorrectly
Predicted
5(0/0)
2-47