MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 145

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The assertion of BKPT should be considered in the following two special cases:
CSR[27–24] indicates the halt source, showing the highest priority source for multiple halt
conditions.
5.5.2 BDM Serial Interface
When the CPU is halted and PST reflects the halt status, the development system can send
unrestricted commands to the debug module. The debug module implements a synchronous
protocol using two inputs (DSCLK and DSI) and one output (DSO), where DSCLK and
2. A hardware breakpoint can be configured to generate a pending halt condition
3. The execution of a HALT instruction immediately suspends execution. Attempting
4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, the halt
• After the system reset signal is negated, the processor waits for 16 processor clock
• The ColdFire architecture also handles a special case of BKPT being asserted while
similar to the assertion of BKPT. This type of halt is always first made pending in
the processor. Next, the processor samples for pending halt and interrupt conditions
once per instruction. When a pending condition is asserted, the processor halts
execution at the next sample point. See Section 5.6.1, “Theory of Operation.”
to execute HALT in user mode while CSR[UHE] = 0 generates a privilege violation
exception. If CSR[UHE] = 1, HALT can be executed in user mode. After HALT
executes, the processor can be restarted by serial shifting a
debug module. Execution continues at the instruction after HALT.
condition is postponed until the processor core samples for halts/interrupts. The
processor samples for these conditions once during the execution of each
instruction. If there is a pending halt condition at the sample time, the processor
suspends execution and enters the halted state.
cycles before beginning reset exception processing. If the BKPT input is asserted
within eight cycles after RSTI is negated, the processor enters the halt state,
signaling halt status (0xF) on the PST outputs. While the processor is in this state,
all resources accessible through the debug module can be referenced. This is the
only chance to force the processor into emulation mode through CSR[EMU].
After system initialization, the processor’s response to the
the set of BDM commands performed while it is halted for a breakpoint.
Specifically, if the PC register was loaded, the
exit halted state and pass control to the instruction address in the PC, bypassing
normal reset exception processing. If the PC was not loaded, the
causes the processor to exit halted state and continue reset exception processing.
the processor is stopped by execution of the STOP instruction. For this case, the
processor exits the stopped mode and enters the halted state, at which point, all BDM
commands may be exercised. When restarted, the processor continues by executing
the next sequential instruction, that is, the instruction following the STOP opcode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 5. Debug Support
Go to: www.freescale.com
GO
command causes the processor to
Background Debug Mode (BDM)
GO
GO
command depends on
command into the
GO
command
5-17