MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 95

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

These registers are described as follows:
3.1.2 General Operation
The MAC unit supports the ColdFire integer multiply instructions (MULS and MULU) and
provides additional functionality for multiply-accumulate operations. The added MAC
instructions to the ColdFire ISA provide for the multiplication of two numbers, followed
by the addition or subtraction of this number to or from the value contained in the
accumulator. The product may be optionally shifted left or right one bit before the addition
or subtraction takes place. Hardware support for saturation arithmetic may be enabled to
minimize software overhead when dealing with potential overflow conditions using signed
or unsigned operands.
These MAC operations treat the operands as one of the following formats:
To maintain compactness, the MAC module is optimized for 16-bit multiplications. Two
16-bit operands produce a 32-bit product. Longword operations are performed by reusing
the 16-bit multiplier array at the expense of a small amount of extra control logic. Again,
the product of two 32-bit operands is a 32-bit result. For longword integer operations, only
the least significant 32 bits of the product are calculated. For fractional operations, the
entire 63-bit product is calculated and then either truncated or rounded to a 32-bit result
using the round-to-nearest (even) method.
Because the multiplier array is implemented in a 3-stage pipeline, MAC instructions can
have an effective issue rate of one clock for word operations, three for longword integer
operations, and four for 32-bit fractional operations. Arithmetic operations use
register-based input operands, and summed values are stored internally in the accumulator.
Thus, an additional MOVE instruction is necessary to store data in a general-purpose
register. MAC instructions can choose the upper or lower word of a register as the input,
which helps filtering operations in which one data register is loaded with input data and
another is loaded with coefficient data. Two 16-bit MAC operations can be performed
without fetching additional operands between instructions by alternating the word choice
• Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to
• Mask register (MASK)—This 16-bit general-purpose register provides an optional
• MAC status register (MACSR)—This 8-bit register defines configuration of the
• Signed integers
• Unsigned integers
• Signed, fixed-point, fractional numbers
accumulate the results of MAC operations.
address mask for MAC instructions that fetch operands from memory. It is useful in
the implementation of circular queues in operand memory.
MAC unit and contains indicator flags affected by MAC instructions. Unless noted
otherwise, the setting of MACSR indicator flags is based on the final result, that is,
the result of the final operation involving the product and accumulator.
Chapter 3. Hardware Multiply/Accumulate (MAC) Unit
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Overview
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