MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 19

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

1-1
1-2
1-3
1-4
2-1
2-2
2-3
2-5
2-6
2-7
2-8
2-9
2-10
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
Figure
Number
MCF5307 Block Diagram............................................................................................. 1-2
UART Module Block Diagram..................................................................................... 1-9
PLL Module ................................................................................................................ 1-12
ColdFire MCF5307 Programming Model .................................................................. 1-13
ColdFire Enhanced Pipeline ....................................................................................... 2-23
ColdFire Multiply-Accumulate Functionality Diagram ............................................. 2-25
ColdFire Programming Model.................................................................................... 2-27
Status Register (SR).................................................................................................... 2-30
Vector Base Register (VBR)....................................................................................... 2-30
Organization of Integer Data Formats in Data Registers............................................ 2-32
Organization of Integer Data Formats in Address Registers ...................................... 2-32
Memory Operand Addressing..................................................................................... 2-33
Exception Stack Frame Form...................................................................................... 2-49
ColdFire MAC Multiplication and Accumulation........................................................ 3-2
MAC Programming Model ........................................................................................... 3-2
SRAM Base Address Register (RAMBAR) ................................................................. 4-3
Unified Cache Organization ......................................................................................... 4-7
Cache Organization and Line Format ........................................................................... 4-8
Cache—A: at Reset, B: after Invalidation, C and D: Loading Pattern ....................... 4-10
Caching Operation ...................................................................................................... 4-11
Write-Miss in Copyback Mode................................................................................... 4-16
Cache Locking ............................................................................................................ 4-20
Cache Control Register (CACR) ................................................................................ 4-21
Access Control Register Format (ACRn) ................................................................... 4-23
An Format .................................................................................................................. 4-24
Cache Line State Diagram—Copyback Mode............................................................ 4-26
Cache Line State Diagram—Write-Through Mode.................................................... 4-26
Processor/Debug Module Interface............................................................................... 5-1
PSTCLK Timing........................................................................................................... 5-3
Example JMP Instruction Output on PST/DDATA...................................................... 5-5
Debug Programming Model ......................................................................................... 5-6
Address Attribute Trigger Register (AATR) ................................................................ 5-7
Address Breakpoint Registers (ABLR, ABHR) ........................................................... 5-9
BDM Address Attribute Register (BAAR)................................................................... 5-9
Configuration/Status Register (CSR).......................................................................... 5-10
Data Breakpoint/Mask Registers (DBR and DBMR)................................................. 5-12
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