MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 92

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Exception Processing Overview
If a ColdFire processor encounters any type of fault during the exception processing of
another fault, the processor immediately halts execution with the catastrophic fault-on-fault
condition. A reset is required to force the processor to exit this halted state.
2-52
Reset
Exception
Unsupported
Instruction
Exception
Exception
Asserting the reset input signal (RSTI) causes a reset exception. Reset has the highest exception
priority; it provides for system initialization and recovery from catastrophic failure. When assertion of
RSTI is recognized, current processing is aborted and cannot be recovered. The reset exception
places the processor in supervisor mode by setting SR[S] and disables tracing by clearing SR[T].
This exception also clears SR[M] and sets the processor’s interrupt priority mask in the SR to the
highest level (level 7). Next, the VBR is initialized to 0x0000_0000. Configuration registers controlling
the operation of all processor-local memories (cache and RAM modules on the MCF5307) are
invalidated, disabling the memories.
Note: Other implementation-specific supervisor registers are also affected. Refer to each of the
modules in this manual for details on these registers.
After RSTI is negated, the processor waits 80 cycles before beginning the actual reset exception
process. During this time, certain events are sampled, including the assertion of the debug
breakpoint signal. If the processor is not halted, it initiates the reset exception by performing two
longword read bus cycles. The longword at address 0 is loaded into the stack pointer and the
longword at address 4 is loaded into the PC. After the initial instruction is fetched from memory,
program execution begins at the address in the PC. If an access error or address error occurs before
the first instruction executes, the processor enters the fault-on-fault halted state.
If the MCF5307 attempts to execute a valid instruction but the required optional hardware module is
not present in the OEP, a non-supported instruction exception is generated (vector 0x61). Control is
then passed to an exception handler that can then process the opcode as required by the system.
Table 2-21. MCF5307 Exceptions (Continued)
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MCF5307 User’s Manual
Description