MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 369

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MCF5307CFT66B

Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307CFT66B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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1
2
Table 17-2 lists signals in alphabetical order by abbreviated name.
Parallel port
Serial clock line
Serial data line
Motorola test mode
Motorola test mode
High impedance
Processor clock out
Processor status
Debug data
Test clock
Test reset/
Development serial
clock
Test mode select/
Breakpoint
Test data input/
Development serial
input
Test data output/
Development serial
output
If there is no arbiter, BG should be tied low; otherwise, it should be negated.
These data pins are sampled at reset for configuration.
AA_CONFIG
ADDR_CONFIG
AS
A[31:0]
Abbreviation
Signal Name
Auto-acknowledge configuration
Address configuration
Address strobe
Address
Table 17-1. MCF5307 Signal Index (Continued)
Table 17-2. MCF507 Alphabetical Signal Index
PP[15:0]
SCL
SDA
MTMOD0
MTMOD[3:1]
HIZ
PSTCLK
PST[3:0]
DDATA[3:0]
TCK
TRST/DSCLK
TMS/BKPT
TDI/DSI
TDO/DSO
Abbreviation
Freescale Semiconductor, Inc.
Section 17.14, “Debug Module/JTAG Signals”
For More Information On This Product,
Section 17.13, “Debug and Test Signals”
Section 17.12, “I
Chapter 17. Signal Descriptions
Signal Name
Go to: www.freescale.com
Interfaces with I/O; multiplexed with
bus address and attribute signals.
Clock signal for I
Serial data port for I
Puts processor in functional or
emulator mode
Reserved
Assertion three-states all outputs
Output clock used for PSTDDATA
Displays captured processor data .
Displays captured processor data
and breakpoint status.
Clock signal for IEEE 1149.1 JTAG
Asynchronous reset for JTAG;
debug module clock input
TMS (JTAG)/hardware breakpoint
(debug)
Multiplexed serial input for the JTAG
or background debug module
Multiplexed serial output for the
JTAG or background debug module
2
C Module Signals”
Function
2
C operation
2
C operation
Clock/reset
Clock/reset
Bus
Bus
Function
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
Driven
Driven
Driven
Reset
Open
Open
Input
drain
drain
User cfg 17-20
I/O
I/O
I/O
Pull-Up Page
I
I
Down
Low
Up
Up
Up
Up
Up
Up
Overview
17-14
17-14
Page
17-9
17-7
17-19
17-19
17-19
17-19
17-20
17-20
17-20
17-20
17-20
17-20
17-21
17-23
17-21
17-22
17-22
17-22
17-5

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