MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 102

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

SRAM Initialization
The mapping of a given access into the RAM uses the following algorithm to determine if
the access hits in the memory:
if (RAMBAR[0] = 1)
if (requested address[31:15] = RAMBAR[31:15])
ASn refers to the five address space mask bits: C/I, SC, SD, UC, and UD.
4.5 SRAM Initialization
After a hardware reset, the contents of the SRAM module are undefined. The valid bit,
RAMBAR[V], is cleared, disabling the SRAM module. If the SRAM requires initialization
with instructions or data, the following steps should be performed:
Remember that the SRAM cannot be accessed by the on-chip DMAs. The on-chip system
configuration allows concurrent core and DMA execution where the core can execute code
4-4
5–1
0
Bits
1. Read the source data and write it to the SRAM. Various instructions support this
2. After the data is loaded into the SRAM, it may be appropriate to revise the
function, including memory-to-memory move instructions and the move multiple
instruction (MOVEM). MOVEM is optimized to generate line-sized burst fetches on
line-aligned addresses, so it generally provides maximum performance.
RAMBAR attribute bits, including the write-protect and address space mask fields.
C/I,
SC,
SD,
UC,
UD
V
Name
if (requested address[14:12] = 0)
Address space masks (ASn). These fields allow certain types of accesses to be masked, or
inhibited from accessing the SRAM module. These bits are useful for power management as
described in Section 4.6, “Power Management.” In particular, C/I is typically set.
The address space mask bits are follows:
C/I = CPU space/interrupt acknowledge cycle mask. Note that C/I must be set if BA = 0.
SC = Supervisor code address space mask
SD = Supervisor data address space mask
UC = User code address space mask
UD = User data address space mask
For each ASn bit:
0 An access to the SRAM module can occur for this address space
1 Disable this address space from the SRAM module. If a reference using this address space is
Valid. Enables/disables the SRAM module. V is cleared at reset.
0 RAMBAR contents are not valid.
1 RAMBAR contents are valid.
made, it is inhibited from accessing the SRAM module and is processed like any other
non-SRAM reference.
Table 4-1. RAMBAR Field Description (Continued)
if (ASn of the requested type = 0)
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For More Information On This Product,
Access is mapped to the RAM module
if (access = read)
if (access = write)
Go to: www.freescale.com
MCF5307 User’s Manual
Read the RAM and return the data
if (RAMBAR[8] = 0)
else Signal a write-protect access error
Write the data into the RAM
Description