MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 385

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

17.14 Debug Module/JTAG Signals
The MCF5307 complies with the IEEE 1149.1a JTAG testing standard. JTAG test pins are
multiplexed with background debug pins. Except for TCK, these signals are selected by the
value of MTMOD0. If MTMOD0 is high, JTAG signals are chosen; if it is low, debug
module signals are chosen. MTMOD0 should be changed only while RSTI is asserted.
17.14.1 Test Reset/Development Serial Clock
If MTMOD0 is high, TRST is selected. TRST asynchronously resets the internal JTAG
controller to the test logic reset state, causing the JTAG instruction register to choose the
bypass instruction. When this occurs, JTAG logic is benign and does not interfere with
normal MCF5307 functionality.
Although TRST is asynchronous, Motorola recommends that it makes an
asserted-to-negated transition only while TMS is held high. TRST has an internal pull-up
resistor so if it is not driven low, it defaults to a logic level of 1. If TRST is not used, it can
be tied to ground or, if TCK is clocked, to V
.
(TRST/DSCLK)
1
2
Rev. B enhancement.
These encodings are asserted for multiple cycles.
Hex
0xC
0xD
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xE
0xF
Table 17-17. Processor Status Signal Encodings
PST[3:0]
Freescale Semiconductor, Inc.
Binary
For More Information On This Product,
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Chapter 17. Signal Descriptions
Go to: www.freescale.com
Continue execution
Begin execution of an instruction
Reserved
Entry into user-mode
Begin execution of PULSE and WDDATA instructions
Begin execution of taken branch or Synch_PC
Reserved
Begin execution of RTE instruction
Begin 1-byte data transfer on DDATA
Begin 2-byte data transfer on DDATA
Begin 3-byte data transfer on DDATA
Begin 4-byte data transfer on DDATA
Exception processing
Emulator mode entry exception processing
Processor is stopped, waiting for interrupt
Processor is halted
DD
. Tying TRST to ground places the JTAG
2
2
Definition
Debug Module/JTAG Signals
2
2
1
17-21