MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 109

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.9 Cache Operation
Figure 4-5 shows the general flow of a caching operation.
The following steps determine if a cache line is allocated for a given address:
To allocate a cache entry, the cache set index selects one of the cache’s 128 sets. The cache
control logic looks for an invalid cache line to use for the new entry. If none is available,
the cache controller uses a pseudo-round-robin replacement algorithm to choose the line to
31
1. The cache set index, A[10:4], selects one cache set.
2. A[31:11] and the cache set index are used as a tag reference or are used to update
3. The four tags from the selected cache set are compared with the tag reference. A
Tag Data/Tag Reference
the cache line tag field. Note that A[31:11] can specify 21 possible addresses that
can be mapped to one of the four ways.
cache hit occurs if a tag matches the tag reference and the V bit is set, indicating that
the cache line contains valid data. If a cacheable write access hits in a valid cache
line, the write can occur to the cache line without having to load it from memory.
If the memory space is copyback, the updated cache line is marked modified
(M = 1), because the new data has made the data in memory out of date. If the
memory location is write-through, the write is passed on to system memory and the
M bit is never used. Note that the tag does not have TT or TM bits.
Address
Freescale Semiconductor, Inc.
A[31:11]
Address
Select
A[10:4]
Set
For More Information On This Product,
Figure 4-5. Caching Operation
11
10
Chapter 4. Local Memory
Go to: www.freescale.com
Index
Set 0
Set 1
Set 127
•
•
•
Comparator
4
3
TAG
TAG
•
•
•
0
STATUS LW0 LW1 LW2 LW3
STATUS LW0 LW1 LW2 LW3
0
•
•
•
1
Way 0
2
Way 1
•
•
•
3
Way 2
•
•
•
Hit 3
Hit 2
Hit 1
Hit 0
Way 3
•
•
•
•
•
•
Logical OR
MUX
Cache Operation
Line Select
Data or
Instruction
Hit
4-11