MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 399

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Basic read and write cycles are used to show a back-to-back cycle, but there is no restriction
as to the type of operations to be placed back to back. The initiation of a back-to-back cycle
is not user definable.
18.4.7 Burst Cycles
The MCF5307 can be programmed to initiate burst cycles if its transfer size exceeds the
size of the port it is transferring to. For example, with bursting enabled, a word transfer to
an 8-bit port would take a 2-byte burst cycle for which SIZ[1:0] = 10 throughout. A line
transfer to a 32-bit port would take a 4-longword burst cycle, for which SIZ[1:0] = 11
throughout.
The MCF5307 bus can support 2-1-1-1 burst cycles to maximize cache performance and
optimize DMA transfers. A user can add wait states by delaying termination of the cycle.
The initiation of a burst cycle is encoded on the size pins. For burst transfers to smaller port
sizes, SIZ[1:0] indicates the size of the entire transfer. For example, if the MCF5307 writes
a longword to an 8-bit port, SIZ[1:0] = 00 for the first byte transfer and does not change.
CSCRs are used to enable bursting for reads, writes, or both. MCF5307 memory space can
be declared burst-inhibited for reads and writes by clearing the appropriate
CSCRx[BSTR,BSTW]. A line access to a burst-inhibited region is broken into separate
port-width accesses. Unlike a burst access, SIZ[1:0] = 11 only for the first port-width
access; for the remaining accesses, SIZ[1:0] reflects the port width, with individual
accesses separated by AS negations. The address changes if internal termination is used but
does not change if external termination is used, as shown in Figure 18-12 and Figure 18-14.
TM[2:0], SIZ[1:0]
A[31:0], TT[1:0]
BE/BWEx
AS, CSx
BCLKO
D[31:0]
R/W
OE
TIP
TS
TA
Freescale Semiconductor, Inc.
Figure 18-11. Back-to-Back Bus Cycles
For More Information On This Product,
S0
S1
Chapter 18. Bus Operation
Go to: www.freescale.com
S2
S3
Read
S4
S5
S0
S1
S2
Write
Data Transfer Operation
S3
S4
S5
18-11