MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 408

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bus Arbitration
18.8 Bus Arbitration
The MCF5307 bus protocol gives either the MCF5307 or an external device access to the
external bus. If more than one external device uses the bus, an external arbiter can prioritize
requests and determine which device is bus master. When the MCF5307 is bus master, it
uses the bus to fetch instructions and transfer data to and from external memory. When an
external device is bus master, the MCF5307 can monitor the external master’s transfers and
interact through its chip-select, DRAM control, and transfer termination signals. See
Section 10.4.1.3, “Chip-Select Control Registers (CSCR0–CSCR7),” and Chapter 11,
“Synchronous/Asynchronous DRAM Controller Module.”
Two-wire bus arbitration is used where the MCF5307 shares the bus with a single external
device. This mode uses BG and BD. The external device can ignore BR. Three-wire mode
is used where the MCF5307 shares the bus with multiple external devices. This requires an
external bus arbiter and uses BG, BD, and BR. In either mode, the MCF5307 bus arbiter
operates synchronously and transitions between states on the rising edge of BCLKO.
Table 18-6 shows the four arbitration states the MCF5307 can be in during bus operation.
18-20
Reset
Implicit
master
State
1.
2.
3.
4.
5.
6.
7.
1.
2.
1.
2.
Drive 0x7FFFFF on A[31:5]
Drive 0x0 on A[1:0]
Drive interrupt level on A[4:2]
Drive R/W to read (R/W = 1)
Drive SIZ[1:0] to indicate byte (SIZ[1:0] = 01)
Drive TT[1:0] and TM[2:0] to indicate interrupt
acknowledge (TT[1:0] = 11; TM[2:0] = interrupt
level)
Assert TS for one BCLKO cycle
Negate TS
Drive TM[2:0] to indicate interrupt
acknowledge (TM[2:0] = interrupt level)
Read and store data (D[31:24])
Recognize the transfer is done
MCF5307
Master
None
Figure 18-23. Interrupt-Acknowledge Cycle Flowchart
MCF5307
driven
driven
Table 18-6. MCF5307 Arbitration Protocol States
Bus
Not
Not
Freescale Semiconductor, Inc.
Negated The MCF5307 enters reset state from any other state when RSTI or
Negated The MCF5307 is bus master (BG input is asserted) but is not ready to
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BD
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software watchdog reset is asserted. If both are negated, the MCF5307
enters implicit or external device mastership state, depending on BG.
begin a bus cycle. It continues to three-state the bus until an internal bus
request.
MCF5307 User’s Manual
1.
2.
3.
Decode address and select the appropriate slave
device.
Drive data on D[31:24]
Assert TA for one BCLKO cycle
Description
SYSTEM