MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 28

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

11-34
11-35
11-36
11-37
12-1
12-2
12-3
12-4
13-1
13-2
13-3
13-5
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
14-13
14-14
15-1
15-2
15-3
16-1
16-2
16-3
16-4
16-5
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
Table
Number
xxviii
DCR Initialization Values......................................................................................... 11-35
DACR Initialization Values...................................................................................... 11-36
DMR0 Initialization Values...................................................................................... 11-37
Mode Register Initialization ..................................................................................... 11-38
DMA Signals .............................................................................................................. 12-2
Memory Map for DMA Controller Module Registers................................................ 12-5
DCRn Field Descriptions............................................................................................ 12-8
DSRn Field Descriptions .......................................................................................... 12-10
General-Purpose Timer Module Memory Map .......................................................... 13-3
TMRn Field Descriptions ........................................................................................... 13-4
TERn Field Descriptions............................................................................................. 13-6
Calculated Time-out Values (90-MHz Processor Clock) ........................................... 13-7
UART Module Programming Model.......................................................................... 14-3
UMR1n Field Descriptions ......................................................................................... 14-5
UMR2n Field Descriptions ......................................................................................... 14-6
USRn Field Descriptions ............................................................................................ 14-7
UCSRn Field Descriptions.......................................................................................... 14-9
UCRn Field Descriptions............................................................................................ 14-9
UIPCRn Field Descriptions ...................................................................................... 14-12
UACRn Field Descriptions ....................................................................................... 14-13
UISRn/UIMRn Field Descriptions ........................................................................... 14-14
UIVRn Field Descriptions ........................................................................................ 14-15
UIPn Field Descriptions............................................................................................ 14-15
UOP1/UOP0 Field Descriptions ............................................................................... 14-16
UART Module Signals ............................................................................................. 14-17
UART Module Initialization Sequence .................................................................... 14-29
Parallel Port Pin Descriptions ..................................................................................... 15-2
PADDR Field Description .......................................................................................... 15-2
Relationship between PADAT Register and Parallel Port Pin (PP) ........................... 15-3
Pins 1–52 (Left, Top-to-Bottom) ................................................................................ 16-1
Pins 53–104 (Bottom, Left-to-Right).......................................................................... 16-3
Pins 105–156 (Right, Bottom-to-Top)........................................................................ 16-4
Pins 157–208 (Top, Right-to-Left) ............................................................................. 16-6
Dimensions ............................................................................................................... 16-11
MCF5307 Signal Index............................................................................................... 17-3
Data Pin Configuration ............................................................................................... 17-6
Bus Cycle Size Encoding............................................................................................ 17-7
Bus Cycle Transfer Type Encoding............................................................................ 17-9
TM[2:0] Encodings for TT = 00 (Normal Access)..................................................... 17-9
TM0 Encoding for DMA as Master (TT = 01) ........................................................... 17-9
TM[2:1] Encoding for DMA as Master (TT = 01) ................................................... 17-10
TM[2:0] Encodings for TT = 10 (Emulator Access) ................................................ 17-10
TM[2:0] Encodings for TT = 11 (Interrupt Level) ................................................... 17-10
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MCF5307 User’s Manual
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