MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 96

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Overview
during the calculations.
The need to move large amounts of data quickly can limit throughput in DSP engines.
However, data can be moved efficiently by using the MOVEM instruction, which
automatically generates line-sized burst references and is ideal for filling registers quickly
with input data, filter coefficients, and output data. Loading an operand from memory into
a register during a MAC operation makes some DSP operations, especially filtering and
convolution, more manageable.
The MACSR has a 4-bit operational mode field and three condition flags. The operational
mode bits control the overflow/saturation mode, whether operands are signed or unsigned,
whether operands are treated as integers or fractions, and how rounding is performed.
Negative, zero and overflow flags are also provided.
The three program-visible MAC registers, a 32-bit accumulator (ACC), the MAC mask
register (MASK), and MACSR, are described in Section 3.1.1, “MAC Programming
Model.”
3.1.3 MAC Instruction Set Summary
The MAC unit supports the integer multiply operations defined by the baseline ColdFire
architecture, as well as the new multiply-accumulate instructions. Table 3-1 summarizes
the MAC unit instruction set.
3.1.4 Data Representation
The MAC unit supports three basic operand types:
Multiply Signed
Multiply Unsigned
Multiply Accumulate
Multiply Accumulate
with Load
Load Accumulator
Store Accumulator
Load MACSR
Store MACSR
Store MACSR to CCR
Load MASK
Store MASK
3-4
Instruction
MULS <ea>y,Dx
MULU <ea>y,Dx
MAC Ry,RxSF
MSAC Ry,RxSF
MAC Ry,RxSF,Rw
MSAC Ry,RxSF,Rw
MOV.L {Ry,#imm},ACC
MOV.L ACC,Rx
MOV.L {Ry,#imm},MACSR Writes a value to the MACSR
MOV.L MACSR,Rx
MOV.L MACSR,CCR
MOV.L {Ry,#imm},MASK
MOV.L MASK,Rx
Freescale Semiconductor, Inc.
Table 3-1. MAC Instruction Summary
Mnemonic
For More Information On This Product,
Go to: www.freescale.com
MCF5307 User’s Manual
Multiplies two signed operands yielding a signed result
Multiplies two unsigned operands yielding an unsigned result
Multiplies two operands, then adds or subtracts the product
to/from the accumulator
Multiplies two operands, then adds or subtracts the product
to/from the accumulator while loading a register with the
memory operand
Loads the accumulator with a 32-bit operand
Writes the contents of the accumulator to a register
Write the contents of MACSR to a register
Write the contents of MACSR to the processor’s CCR register
Writes a value to MASK
Writes the contents of MASK to a register
Description