MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 406

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Interrupt Exceptions
The MCF5307 has the following two levels of interrupt masking:
The MCF5307 continuously samples and synchronizes external interrupt inputs. An
interrupt request must be held for at least two consecutive BCLKO periods to be considered
valid. To guarantee that the interrupt is recognized, the request level must be maintained
until the MCF5307 acknowledges the interrupt with an interrupt-acknowledge cycle.
The MCF5307 takes an interrupt exception for a pending interrupt within one instruction
boundary after processing any higher-priority pending exception. Thus, the MCF5307
executes at least one instruction in an interrupt exception handler before recognizing
another interrupt request.
If autovector generation is used for internal interrupts (ICRn[AVEC] = 1), the interrupt
acknowledge vector is generated internally and no interrupt acknowledge cycle is generated
on the external bus.
If autovector generation is used for external interrupts, no interrupt acknowledge cycle is
shown on the external bus (AS is not asserted) unless AVR[BLK] is 0. Consequently, the
external interrupt must be cleared in the interrupt service routine. See Section 9.2.2,
“Autovector Register (AVR).”
18.7.1 Level 7 Interrupts
Level 7 interrupts are nonmaskable and are handled differently than other interrupts.
Level 7 interrupts are edge triggered by a transition from a lower priority request to the
level 7 request. Interrupts at all other levels are level sensitive. Therefore, if IRQ7 remains
asserted, the MCF5307 recognizes only one level 7 interrupt because only one transition
from a lower level request to a level 7evel 7 request occurred. For the processor to
recognize two consecutive level 7 interrupts, one of the following must occur:
18-18
• Interrupt mask registers in the SIM compare interrupt inputs with programmable
• The status register uses a 3-bit interrupt priority mask. The core recognizes only
interrupt mask levels. The SIM outputs only unmasked interrupts.
interrupt requests of higher priority than the value in the mask. See Section 2.2.2.1,
“Status Register (SR).”
To mask a level 1–6 interrupt source, write a higher-level SR
interrupt mask before setting IMR. Then restore the mask to its
previous value. Do not mask a level 7 interrupt source.
Interrupt levels 1–7 are level-sensitive. Level 7 is also
edge-triggered. See Section 18.7.1, “Level 7 Interrupts.”
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MCF5307 User’s Manual
NOTE:
NOTE: