MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 188

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Programming Model
6.2.5 System Protection Control Register (SYPCR)
The SYPCR, Figure 6-5, controls the software watchdog timer, timeout periods, and
software watchdog timer transfer acknowledge. The SYPCR can be read at any time, but
can be written only if a software watchdog timer IRQ is not pending. At system reset, the
software watchdog timer is disabled.
Table 6-4 describes SYPCR fields.
6-8
Bits
4–3
7
6
5
1. Disable the software watchdog timer by clearing SYPCR[SWE].
2. Reset the counter by writing 0x55 and then 0xAA to SWSR.
3. Update SYPCR[SWT,SWP].
4. Reenable the watchdog timer by setting SYPCR[SWE]. This can be done in step 3.
Address
Name
SWRI
Reset
SWE
SWP
SWT
Field
R/W
Figure 6-5. System Protection Control Register (SYPCR)
SWE
Software watchdog timer enable
0 Software watchdog timer disabled
1 Software watchdog timer enabled
Software watchdog reset/interrupt select
0 If a timeout occurs, the watchdog timer generates an interrupt to the core processor at the
1 The software watchdog timer causes soft reset to be asserted for all modules of the part
Software watchdog prescaler. This bit interacts with SYPCR[SWT].
0 Software watchdog timer clock not prescaled.
1 Software watchdog timer clock prescaled by 8192.
Software watchdog timing delay. SWT and SWP select the timeout period for the watchdog
timer. At system reset, the software watchdog timer is set to the minimum timeout period.
SWP = 0
00 2
01 2
10 2
11 2
Note that if SWP and SWT are modified to select a new software timeout, the software service
sequence must be performed (0x55 followed by 0xAA written to the SWSR) before the new
timeout period takes effect.
7
level programmed into ICR0[IL].
except for the PLL (reset mode selects, such as PP_RESET_SEL or chip-select settings,
should not change).
9
11
13
15
/system frequency
/system frequency
/system frequency
/system frequency
Freescale Semiconductor, Inc.
SWRI
Table 6-4. SYPCR Field Descriptions
For More Information On This Product,
6
Go to: www.freescale.com
SWP
MCF5307 User’s Manual
5
SWP = 1
00 2
01 2
10 2
11 2
MBAR + 0x01
4
0000_0000
22
24
26
28
/system frequency
/system frequency
/system frequency
/system frequency
SWT
R/W
Description
3
SWTA
2
SWTAVAL
1
—
0