MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 215

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Freescale Semiconductor, Inc.
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I
C Programming Examples
8.6.6 Slave Mode
In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be
tested to check if a calling of its own address has just been received. If IAAS is set, software
should set the transmit/receive mode select bit (I2CR[MTX]) according to the I2SR[SRW].
Writing to the I2CR clears the IAAS automatically. The only time IAAS is read as set is
from the interrupt at the end of the address cycle where an address match occurred;
interrupts resulting from subsequent data transfers will have IAAS cleared. A data transfer
can now be initiated by writing information to I2DR for slave transmits, or read from I2DR
in slave-receive mode. A dummy read of I2DR in slave/receive mode releases SCL,
allowing the master to send data.
In the slave transmitter routine, I2SR[RXAK] must be tested before sending the next byte
of data. Setting RXAK means an end-of-data signal from the master receiver, after which
software must switch it from transmitter to receiver mode. Reading I2DR then releases SCL
so that the master can generate a STOP signal.
8.6.7 Arbitration Lost
If several devices try to engage the bus at the same time, one becomes master. Hardware
immediately switches devices that lose arbitration to slave receive mode. Data output to
SDA stops, but SCL is still generated until the end of the byte during which arbitration is
lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with
I2SR[IAL] = 1 and I2CR[MSTA] = 0.
If a device that is not a master tries to transmit or do a START, hardware inhibits the
transmission, clears MSTA without signalling a STOP, generates an interrupt to the CPU,
and sets IAL to indicate a failed attempt to engage the bus. When considering these cases,
the slave service routine should first test IAL and software should clear it if it is set.
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Chapter 8. I
C Module
8-13
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