MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 17

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MCF5307CFT66B

Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307CFT66B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

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Quantity
Price
Part Number:
MCF5307CFT66B
Manufacturer:
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Part Number:
MCF5307CFT66B
Manufacturer:
Freescale Semiconductor
Quantity:
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18.1
18.2
18.3
18.4
18.4.1
18.4.2
18.4.3
18.4.4
18.4.5
18.4.6
18.4.7
18.4.7.1
18.4.7.2
18.4.7.3
18.4.7.4
18.5
18.6
18.7
18.7.1
18.7.2
18.8
18.8.1
18.9
18.9.1
18.9.2
18.10
18.10.1
18.10.2
19.1
19.2
19.3
19.4
19.4.1
19.4.2
19.4.3
Paragraph
Number
Features ............................................................................................................. 18-1
Bus and Control Signals ................................................................................... 18-1
Bus Characteristics............................................................................................ 18-2
Data Transfer Operation ................................................................................... 18-3
Misaligned Operands ...................................................................................... 18-16
Bus Errors ....................................................................................................... 18-17
Interrupt Exceptions........................................................................................ 18-17
Bus Arbitration................................................................................................ 18-20
General Operation of External Master Transfers............................................ 18-21
Reset Operation............................................................................................... 18-33
Overview........................................................................................................... 19-1
TAP Controller.................................................................................................. 19-3
JTAG Register Descriptions ............................................................................. 19-4
JTAG Signal Descriptions ............................................................................... 19-2
Bus Cycle Execution..................................................................................... 18-4
Data Transfer Cycle States ........................................................................... 18-5
Read Cycle.................................................................................................... 18-7
Write Cycle ................................................................................................... 18-8
Fast-Termination Cycles............................................................................... 18-9
Back-to-Back Bus Cycles ........................................................................... 18-10
Burst Cycles................................................................................................ 18-11
Level 7 Interrupts........................................................................................ 18-18
Interrupt-Acknowledge Cycle..................................................................... 18-19
Bus Arbitration Signals............................................................................... 18-21
Two-Device Bus Arbitration Protocol (Two-Wire Mode) ......................... 18-25
Multiple External Bus Device Arbitration Protocol (Three-Wire Mode)... 18-29
Master Reset ............................................................................................... 18-34
Software Watchdog Reset........................................................................... 18-35
IDCODE Register ......................................................................................... 19-6
JTAG Boundary-Scan Register .................................................................... 19-7
JTAG Instruction Shift Register .................................................................. 19-5
Line Transfers ......................................................................................... 18-12
Line Read Bus Cycles............................................................................. 18-12
Line Write Bus Cycles............................................................................ 18-14
Transfers Using Mixed Port Sizes .......................................................... 18-15
IEEE 1149.1 Test Access Port (JTAG)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
CONTENTS
Bus Operation
Chapter 18
Chapter 19
Contents
Title
Number
Page
xvii

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