MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 9

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MCF5307CFT66B

Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307CFT66B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5307CFT66B
Manufacturer:
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Quantity:
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Part Number:
MCF5307CFT66B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
5.5.3.3.4
5.5.3.3.5
5.5.3.3.6
5.5.3.3.7
5.5.3.3.8
5.5.3.3.9
5.5.3.3.10
5.5.3.3.11
5.5.3.3.12
5.5.3.3.13
5.6
5.6.1
5.6.1.1
5.6.2
5.7
5.8
5.8.1
5.8.2
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.10.1
6.2.10.1.1
6.2.10.1.2
Paragraph
Number
Real-Time Debug Support ................................................................................ 5-39
Motorola-Recommended BDM Pinout............................................................. 5-42
Processor Status, DDATA Definition............................................................... 5-42
Features ............................................................................................................... 6-1
Programming Model ........................................................................................... 6-3
Theory of Operation...................................................................................... 5-40
Concurrent BDM and Processor Operation .................................................. 5-41
User Instruction Set ...................................................................................... 5-43
Supervisor Instruction Set............................................................................. 5-46
SIM Register Memory Map............................................................................ 6-3
Module Base Address Register (MBAR) ....................................................... 6-4
Reset Status Register (RSR) ........................................................................... 6-5
Software Watchdog Timer.............................................................................. 6-6
System Protection Control Register (SYPCR) ............................................... 6-8
Software Watchdog Interrupt Vector Register (SWIVR)............................... 6-9
Software Watchdog Service Register (SWSR)............................................... 6-9
PLL Clock Control for CPU STOP Instruction ............................................ 6-10
Pin Assignment Register (PAR) ................................................................... 6-10
Bus Arbitration Control ................................................................................ 6-11
Emulator Mode ......................................................................................... 5-41
Default Bus Master Park Register (MPARK) .......................................... 6-11
Write Memory Location (
Dump Memory Block (
Fill Memory Block (
Resume Execution (
No Operation (
Synchronize PC to the PST/DDATA Lines (
Read Control Register (
Write Control Register (
Read Debug Module Register (
Write Debug Module Register (
Arbitration for Internally Generated Transfers (MPARK[PARK])...... 6-12
Arbitration between Internal and External Masters
for Accessing Internal Resources ......................................................... 6-14
Freescale Semiconductor, Inc.
System Integration Module (SIM)
For More Information On This Product,
Go to: www.freescale.com
NOP
CONTENTS
SIM Overview
) .............................................................................. 5-34
Chapter 6
GO
FILL
Contents
Part II
)........................................................................ 5-33
Title
DUMP
RCREG
WCREG
) ..................................................................... 5-31
WRITE
) .............................................................. 5-29
) ............................................................ 5-36
RDMREG
) .......................................................... 5-37
WDMREG
) ......................................................... 5-27
) ............................................. 5-38
) ........................................... 5-39
SYNC
_
PC
) ....................... 5-35
Number
Page
ix

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