MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 174

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Processor Status, DDATA Definition
1
2
3
Exception Processing
The PST/DDATA specification for the reset exception is shown below:
Exception Processing PST = 0xC,
The initial references at address 0 and 4 are never captured nor displayed since these
accesses are treated as instruction fetches.
For all types of exception processing, the PST = 0xC value is driven at all times, unless the
PST output is needed for one of the optional marker values or for the taken branch indicator
(0x5).
5.8.2 Supervisor Instruction Set
The supervisor instruction set has complete access to the user mode instructions plus the
opcodes shown below. The PST/DDATA specification for these opcodes is shown in
Table 5-23.
5-46
unlk
wddata.b
wddata.l
wddata.w
cpushl
halt
move.w
move.w
For JMP and JSR instructions, the optional target instruction address is displayed only for those effective
address fields defining variant addressing modes. This includes the following <ea>x values: (An), (d16,An),
(d8,An,Xi), (d8,PC,Xi).
For Move Multiple instructions (MOVEM), the processor automatically generates line-sized transfers if the
operand address reaches a 0-modulo-16 boundary and there are four or more registers to be transferred. For
these line-sized transfers, the operand data is never captured nor displayed, regardless of the CSR value.
The automatic line-sized burst transfers are provided to maximize performance during these sequential
memory access operations.
During normal exception processing, the PST output is driven to a 0xC indicating the exception processing
state. The exception stack write operands, as well as the vector read and target address of the exception
handler may also be displayed.
Instruction
Instruction
Table 5-22. PST/DDATA Specification for User-Mode Instructions (Continued)
Table 5-23. PST/DDATA Specification for Supervisor-Mode Instructions
Ax
<ea>y
<ea>y
<ea>y
SR,Dx
{Dy,#imm},SR
Operand Syntax
Operand Syntax
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PST = 0x5,{PST = [0x9AB], DD = target} // PC of handler
PST = 0xC, {PST = 0xB, DD = destination},// stack frame
PST = 0x5, {PST = [0x9AB], DD = target}// PC of handler
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PST = 0x1, {PST = 0xB, DD = destination operand}
PST = 0x4, {PST = 0x8, DD = source operand
PST = 0x4, {PST = 0xB, DD = source operand
PST = 0x4, {PST = 0x9, DD = source operand
PST = 0x1
PST = 0x1,
PST = 0xF
PST = 0x1
PST = 0x1, {PST = 3}
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MCF5307 User’s Manual
{PST = 0xB, DD = destination},// stack frame
{PST = 0xB, DD = source},// vector read
PST/DDATA
PSTDDATA