MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 316

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MCF5307CFT66B

Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307CFT66B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

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Part Number:
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Quantity:
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Register Descriptions
14.3.2 UART Mode Register 2 (UMR2n)
UART mode registers 2 (UMR2n) control UART module configuration. UMR2n can be
read or written when the mode register pointer points to it, which occurs after any access to
UMR1n. UMR2n accesses do not update the pointer.
Table 14-3 describes UMR2n fields.
Bits
7–6
14-6
Address
5
4
Reset
Field
R/W
TxRTS Transmitter ready-to-send. Controls negation of RTS to automatically terminate a message
TxCTS Transmitter clear-to-send. If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the
Name
CM
Channel mode. Selects a channel mode. Section 14.5.3, “Looping Modes,” describes individual
modes.
00 Normal
01 Automatic echo
10 Local loop-back
11 Remote loop-back
transmission. Attempting to program a receiver and transmitter in the same channel for RTS control is
not permitted and disables RTS control for both.
0 The transmitter has no effect on RTS.
1 In applications where the transmitter is disabled after transmission completes, setting this bit
transmitter.
0 CTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to
7
automatically clears UOP[RTS] one bit time after any characters in the channel transmitter shift and
holding registers are completely sent, including the programmed number of stop bits.
send a character. If CTS is asserted, the character is sent; if it is negated, the channel TxD remains
in the high state and transmission is delayed until CTS is asserted. Changes in CTS as a character is
being sent do not affect its transmission.
CM
MBAR + 0x1C0, 0x200. After UMR1n is read or written, the pointer points to UMR2n.
Figure 14-3. UART Mode Register 2 (UMR2n)
6
Freescale Semiconductor, Inc.
Table 14-3. UMR2n Field Descriptions
For More Information On This Product,
TxRTS
5
Go to: www.freescale.com
MCF5307 User’s Manual
TxCTS
4
0000_0000
Description
R/W
3
SB
0

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