MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 105

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The cache supports operation of copyback, write-through, or cache-inhibited modes. The
cache lock feature can be used to guarantee deterministic response for critical code or data
areas.
A nonblocking cache services read hits or write hits from the processor while a fill (caused
by a cache allocation) is in progress. As Figure 4-2 shows, instruction and data accesses
use a single bus connected to the cache.
All addresses from the processor to the cache are physical addresses. A cache hit occurs
when an address matches a cache entry. For a read, the cache supplies data to the processor.
For a write, the processor updates the cache. If an access does not match a cache entry
(misses the cache) or if a write access must be written through to memory, the cache
performs a bus cycle on the internal bus and correspondingly on the external bus by way of
the system integration module (SIM).
The SRAM module does not implement bus snooping; cache coherency with other possible
bus masters must be maintained in software.
4.8 Cache Organization
A four-way set associative cache is organized as four ways (levels). There are 128 sets in
the 8-Kbyte cache with each line containing 16 bytes (4 longwords). Entire cache lines are
loaded from memory by burst-mode accesses that cache 4 longwords of data or
instructions. All 4 longwords must be loaded for the cache line to be valid.
Figure 4-3 shows cache organization as well as terminology used.
Processor
ColdFire
Core
Control
Address
Data
Freescale Semiconductor, Inc.
Figure 4-2. Unified Cache Organization
For More Information On This Product,
Directory Array
Address Path
Control Logic
Chapter 4. Local Memory
Go to: www.freescale.com
Cache
Data Path
Data Array
Address
Control
Data
Integration
System
Module
(SIM)
Cache Organization
Address/
External
Control
Data
Bus
4-7