TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 102

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

7.3
Function
RB000
7.3.3
7.3.4
checked by reading VDCR1<VDxF> and VDCR1<VDxSF>.
(VDxLVL), VDCR1<VDxF> is set to "1" and is held in this state. VDCR1<VDxF> is not cleared to "0" when
the supply voltage (VDD) becomes equal to or higher than the detection voltage (VDxLVL).
To clear VDCR1<VDxF>, "0" must be written to it.
(VDxLVL), VDCR1<VDxSF> is set to "1". When the supply voltage (VDD) becomes equal to or higher than
the detection voltage (VDxLVL), VDCR1<VDxSF> is cleared to "0".
Selecting the detection voltage level
Voltage detection flag and voltage detection status flag
Note 1: When the supply voltage (VDD) becomes lower than the detection voltage (VDxLVL) in the STOP, IDLE0 or
Note 2: Depending on the voltage detection timing, the voltage detection status flag (VDxSF) may be changed earlier
Select a detection voltage at VDCR1<VDxLVL>.
The magnitude relation between the supply voltage (VDD) and the detection voltage (VDxLVL) can be
If VDCR2<VDxEN> is set at "1", when the supply voltage (VDD) becomes lower than the detection voltage
When VDCR2<VDxEN> is cleared to "0" after VDCR1<VDxF> is set to "1", the previous state is still held.
If VDCR2<VDxEN> is set at "1", when the supply voltage (VDD) becomes lower than the detection voltage
Unlike VDCR1<VDxF>, VDCR1<VDxSF> does not hold the set state.
Voltage detection reset signal
detection reset signal is generated continuously as long as the supply voltage (VDD) is lower than the
detection voltage (VDxLVL).
SLEEP0 mode, the voltage detection flag and the voltage detection status flag are changed after the oper-
ation mode is returned to NORMAL or SLOW mode.
than the voltage detection flag (VDxF) by a maximum of 2/fcgck[s].
Detection voltage level
VDCR1 and VDCR2 are initialized by a power-on reset or an external reset input only. A voltage
VDCR2<VDxEN>
VDD level
Figure 7-3 Voltage Detection Reset Signal
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TMP89FS60