TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 61

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RB000
2.4.4.7
2.4.4.8
2.4.4.9
ming data need to be reloaded by generating an internal factor reset, such as a system clock reset, and activating
the warm-up operation again.
circuit and power-on reset circuit does not satisfy the characteristic specified in the electric characteristics.
Design the system so that the system will not be damaged in such a case.
memory while it is on standby.
reset, except the power-on reset, the factor which causes a reset can be detected.
set.
factor reset detection status register is clear to "0". IRSTSR<FCLR> is cleared to "0" automatically after
initializing the internal factor reset detection status register.
is turned on and the warm-up operation that follows reset release is finished.
connect a pull-up resistor for a port. Then set SYSCR3<RSTDIS> to "1" and write 0xB2 to SYSCR4. This
disables the external reset function and makes the external reset input pin usable as a normal port.
connect the pull-up resistor to put the pin to the input mode. Then clear SYSCR3<RSTDIS> to "0" and write
0xB2 to SYSCR4. This enables the external reset function and makes the pin usable as the external reset input
pin.
Note 1: Care must be taken in system designing since the IRSTSR may not fulfill its functions due to disturbing
Note 2: In the case of 89FS60, if setting "1" to IRSTSR<FCLR>, each flag of IRSTSR register is cleared to "0"
Note 3: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR<FCLR>
Note 1: If you switch the external reset input pin to a port or switch the pin used as a port to the external reset
Note 2: If the external reset input is used as a port, the statement which clears SYSCR3<RSTDIS> to "0" is not
Note 3: After SYSCR3<RSTDIS> is modified, SYSCR4 should be written 0xB2 (Enable code for
When IRSTSR<TRMDS> is read as "1" in the initialize routine immediately after reset release, the trim-
If IRSTSR<TRMDS> is still set to "1" after repeated reading, the detection voltage of the voltage detection
The flash standby reset is an internal factor reset generated by the reading or writing of data of the flash
Refer to "Flash Memory".
By reading the internal factor reset detection status register IRSTSR after the release of an internal factor
The internal factor reset detection status register is initialized by an external reset input or power-on re-
Set IRSTSR<FCLR> to "1" and write 0x71 to SYSCR4. This enables IRSTSR<FCLR> and the internal
To use the external reset input pin as a port, keep the external reset input pin at the "H" level until the power
After the warm-up operation that follows reset release is finished, set P1PU0 to "1" and P1CR0 to "0", and
To use the pin as an external reset pin when it is used as a port, set P1PU0 to "1" and P1CR0 to "0" and
Flash standby reset
Internal factor reset detection status register
How to use the external reset input pin as a port
noise and other effects.
without setting "0x71" to SYSCR4. Nevertheless, in order to keep software compatibility with other prod-
uct, it is recommended to describe the program code that set "0x71" to IRSTSR<FCLR> after setting "1"
to IRSTSR<FCLR>.
in NORMAL mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> may be
enabled at unexpected timing.
input pin, do it when the pin is stabilized at the "H" level. Switching the pin function when the "L" level is
input may cause a reset.
written in a program. By the abnormal execution of program, the external reset input set as a port may
be changed as the external reset input at unexpected timing.
SYSCR3<RSTDIS>) in NORMAL1 mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise,
SYSCR3<RSTDIS> may be enabled at unexpected timing.
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TMP89FS60