TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 249

no-image

TMP89xy60UG/FG

Manufacturer Part Number
TMP89xy60UG/FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP89xy60UG/FG

Package
LQFP64/QFP64
Rom Types (m=mask,p=otp,f=flash)
M/F
Rom Size
32/60
Ram Size
3K
Driver Led
8
Driver Lcd
-
Spi/sio Channels
-
Uart/sio Channels
2
I2c/sio Channels
1
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
16
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
2
Timer Counter 8-bit Channel
4
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
Y
Number Of I/o Ports
58
Power Supply (v)
4.3 to 5.5
RA001
16.10
Table 16-8 Received Data Noise Rejection Time
RXDNC
00
01
10
11
in Table 16-8.
RT clock
RXD0 pin
Internal received
data
Shift register
Note 1: The transfer base clock frequency is the clock frequency selected at UARTCR1<BRG>.
When noise rejection is enabled at UART0CR2<RXDNC>, the time of pulses to be regarded as signals is as shown
Received Data Noise Rejection
2 × (UART0DR+1)/(Transfer base clock frequency)
4 × (UART0DR+1)/(Transfer base clock frequency)
(UART0DR+1)/(Transfer base clock frequency)
Noise
Noise is removed
Noise rejection time [s]
No noise rejection
Figure 16-9 Received Data Noise Rejection
A falling edge
is detected
15 14 13 12 11 10 9
Start bit
Start bit
When the noise rejection
circuit is used
Page 233
because the start bit is 0
Receiving continues
8
7
6
5
2 × (UART0DR+1)/(Transfer base clock frequency)
4 × (UART0DR+1)/(Transfer base clock frequency)
8 × (UART0DR+1)/(Transfer base clock frequency)
4
Time of pulses to be regarded as signals
3
2
1 0 15 14 13 12 11 10 9
Bit 0
Bit 0
The received data is taken into
-
the shift register
8
TMP89FS60
7
6
5
Bit 0
4 3

Related parts for TMP89xy60UG/FG