TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 154

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

11.2
Control
RA001
11.2
Divider output control register
(0x0038)
DVOCR
The divider output is controlled by the divider output control register (DVOCR).
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: DVOCR<DVOEN> is cleared to "0" when the operation is switched to STOP or IDLE0/SLEEP0 mode. DVOCR<DVOCK>
Note 3: When SYSCR1<DV9CK> is "1" in the NORMAL 1/2 or IDLE 1/2 mode, the DVO frequency is subject to some fluctuations
Note 4: Bits 7 to 3 of DVOCR are read as "0".
Control
DVOEN
DVOCK
Read/Write
Bit Symbol
After reset
holds the value.
to synchronize fs and fcgck.
Enables/disables
the divider output
Selects the divider output frequency
Unit: [Hz]
R
7
0
-
R
6
0
-
R
5
0
0: Disable the divider output
1: Enable the divider output
Page 138
-
00
01
10
11
DV9CK=0
fcgck/2
fcgck/2
fcgck/2
fcgck/2
R
4
0
-
NORMAL 1/2, IDLE 1/2 mode
12
11
10
9
R
3
0
-
DV9CK=1
Reserved
DV0EN
fs/2
fs/2
fs/2
R/W
2
0
5
4
3
1
0
TMP89FS60
DVOCK
SLOW1/2
Reserved
SLEEP1
R/W
mode
fs/2
fs/2
fs/2
5
4
3
0
0