TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 302

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

18.4
Functions
RA002
18.4.12
18.4.13
SCL (Bus)
SDA (Bus)
SDA0 pin
SBI0SR2<AD0>
INTSBI0 Interrupt request
SCL0 (Bus)
SDA0 (Bus)
SDA0 pin
SBI0SR2<AAS>
INTSBI0 Interrupt request
data matches the slave address setting by I2C0AR<SA> with SBI0CR1<NOACK> set at "0" and the I
mode is active (I2C0AR<ALS>="0").
tections. SBI0SR2<AAS> remains at "0" even if a "GENERAL CALL" is received or the same slave address as
the I2C0AR<SA> set value is received.
is set to "1" after receiving the first 1-word of data. SBI0SR2<AAS> is cleared to "0" by writing data to the
SBI0DBR or reading data from the SBI0DBR.
is "0" immediately after a start condition) in a slave mode.
tections. SBI0SR2<AD0> remains at "0" even if a "GENERAL CALL" is received.
In the slave mode, SBI0SR2<AAS> is set to "1" when the received data is "GENERAL CALL" or the received
Setting SBI0CR1<NOACK> to "1" disables the subsequent slave address match and GENERAL CALL de-
When a serial bus interface circuit operates in the free data format (I2C0AR<ALS>= "1"), SBI0SR2<AAS>
SBI0SR2<AD0> is set to "1" when SBI0CR1<NOACK> is "0" and GENERAL CALL (all 8-bit received data
Setting SBI0CR1<NOACK> to "1" disables the subsequent slave address match and GENERAL CALL de-
SBI0SR2<AD0> is cleared to "0" when a start or stop condition is detected on a bus.
Figure 18-14 Changes in the Slave Address Match Detection Monitor
Slave address match detection monitor
GENERAL CALL detection monitor
Figure 18-15 Changes in the GENERAL CALL Detection Monitor
Start condition
1
Start condition
SA6
1
2
SA5
2
3
SA4
GENERAL CALL
3
4
Slave address + Direction bit
Page 286
SA3
4
5
SA2
5
6
SA1
6
7
Output of an acknowledge signal
SA0
7
Writing or reading SBI0DBR
8
Output of an acknowledge signal
R/W
8
9
9
Stop condition
TMP89FS60
2
C bus