TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 38

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

2.3
System clock controller
RB000
2.3.5
2.3.4.2
Note 2: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The warm-up time contains
frequency clocks, and switches the main system clock (fm).
modes are controlled by the system control registers (SYSCR1 and SYSCR2).
Operation mode control circuit
The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-
There are three operating modes: the single-clock mode, the dual-clock mode and the STOP mode. These
Figure 2-7 shows the operating mode transition diagram.
oscillation becomes stable, at a mode change from NORMAL1 to NORMAL2 or from SLOW1 to SLOW2.
stopped oscillation circuit to start oscillation and the 14-stage counter to start counting the selected input
clock.
is stopped and the counter is cleared.
WUCCR<WUCRST> is cleared to "0".
restart the warm-up operation, SYSCR2<XEN> or SYSCR2<XTEN> must be cleared to "0".
errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. Set the sufficient time for
the oscillation start property of the oscillator.
The warm-up counter serves to secure the time after the oscillation is enabled by the software before the
Select the input clock to the frequency division circuit at WUCCR<WUCSEL>.
Select the input clock to the 14-stage counter at WUCCR<WUCDIV>.
After the warm-up time is set at WUCDR, setting SYSCR2<XEN> or SYSCR2<XTEN> to "1" allows the
When the upper 8 bits of the counter become equal to WUCDR, an INTWUC interrupt occurs, counting
Set WUCCR<WUCRST> to "1" to discontinue the warm-up operation.
By setting it to "1", the count-up operation is stopped, the warm-up counter is cleared, and
SYSCR2<XEN> and SYSCR2<XTEN> hold the values when WUCCR<WUCRST> is set to "1". To
Warm-up counter operation when the oscillation is enabled by the software
Note:The warm-up counter starts counting when SYSCR2<XEN> or SYSCR2<XTEN> is changed from "0"
Note:The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The
to "1". The counter will not start counting by writing "1" to SYSCR2<XEN> or SYSCR2<XTEN> when
it is in the state of "1".
warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit
becomes stable. Set the sufficient time for the oscillation start property of the oscillator.
<WUCSEL>
WUCCR
0
1
<WUCDIV>
WUCCR
00
01
10
11
00
01
10
11
Counter input
Page 22
fc / 2
fc / 2
fs / 2
fs / 2
clock
fc / 2
fs / 2
fc
fs
2
3
2
3
2
2
2
2
2
2
2
2
6
7
8
9
6
7
8
9
/ fc to 255 x 2
/ fc to 255 x 2
/ fc to 255 x 2
/ fc to 255 x 2
/ fs to 255 x 2
/ fs to 255 x 2
/ fs to 255 x 2
/ fs to 255 x 2
Warm-up time
6
7
8
9
6
7
8
9
/ fc
/ fc
/ fc
/ fc
/ fs
/ fs
/ fs
/ fs
TMP89FS60