TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 348

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

21.5
Access to the Flash Memory Area
RA006
Note 1: If the RAM loader is used in serial PROM mode, the BOOTROM disables (DI) a maskable interrupt, and
Note 2: If a certain interrupt is used in the RAM loader program, a vector address corresponding to that interrupt
Note 3: Do not set SYSCR3<RVCTR> to "0" by using the RAM loader program. If an interrupt occurs with
Example: A case in which a program is transferred to RAM, the sector erase is performed on 0xE000 through 0xEFFF
main section code abs = 0x0100
; #### Set a nonmaskable interrupt vector inside the RAM area #### (step 3)
; #### Sector erase and write process ####
; Sector erase process (step 5)
; Write process (step 8)
; #### Execute the next main program ####
; #### Program to be executed in RAM ####
sSectorErase:
; Sector erase proc-
ess
; Write process
sByteProgram:
10. Set FLSCR1<FLSMD> to "0y010", and then set "0xD5" on FLSCR2<CR1EN> (to disable the
the interrupt vector area is designated as a RAM area (SYSCR3<RVCTR>="1"). Considering that a
nonmaskable interrupt may be generated unexpectedly, it is recommended that vector addresses cor-
responding these interrupts (INTUNDEF, INTSWI: 0x01F8 to 0x01F9, WDT: 0x01FC to 0x01FD) be
established and that an interrupt service routine be defined inside the RAM area.
and the interrupt service routine must be established inside the RAM area. In this case, it is recommended
that a nonmaskable interrupt be handled as explained in Note 1.
SYSCR3<RVCTR> set to "0", the BOOTROM area is referenced as a vector address and, therefore, the
program will not function properly.
execution of the command sequence).
in the code area, and then data of 0x3F is written to 0xE500.
If nonmaskable interrupts (INTSWI, INTUNDEF or INTWDT) occur, system clock reset is generated.
LD
LDW
LD
LDW
LD
LD
LD
LD
CALL
LD
LD
LD
CALL
:
J
CALL
LD
LD
LD
LD
LD
LD
J
CALL
LD
LD
LD
LD
HL,0x01FC
(HL),sINTSWI
HL,0x01F8
(HL),sINTWDT
HL,0xF555
DE,0xFAAA
C,0x00
IX,0xE000
sSectorErase
C,0x00
IX,0xE500
B,0x3F
sByteProgram
:
XXXXX
sAddConv
(HL),E
(DE),L
(HL),0x80
(HL),E
(DE),L
(IX),0x30
sRAMopEnd
sAddConv
(HL),E
(DE),L
(HL),0xA0
(IX),B
Page 332
; Set INTUNDEF and INTSWI interrupt vectors
; Set INTWDT interrupt vector
; Variable for command sequence
; Variable for command sequence
; Set upper address
; Set middle and lower addresses
; Perform a sector erase (0xE000)
; Set upper address
; Set middle and lower addresses
; Data to be written
; Write process (0xE500)
; Execute the main program
; Address conversion process
; 1st Bus Write Cycle (note 1)
; 2nd Bus Write Cycle (note 1)
; 3rd Bus Write Cycle (note 1)
; 4th Bus Write Cycle (note 1)
; 5th Bus Write Cycle (note 1)
; 6th Bus Write Cycle (note 1)
; Convert address
; 1st Bus Write Cycle (note 1)
; 2nd Bus Write Cycle (note 1)
; 3rd Bus Write Cycle (note 1)
; 4th Bus Write Cycle (note 1)
TMP89FS60