TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 257

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA001
16.12.5
16.12.6
UART0CR1<TXE>
TXD0 pin input
UART0SR<TBFL>
UART0SR<TBSY>
INTTXD0 interrupt
request
Writing of TD0BUF
UART0CR1<TXE>
TXD0 pin input
UART0SR<TBFL>
UART0SR<TBSY>
INTTXD0 interrupt
request
Writing of TD0BUF
UART0SR<TBSY> is cleared to "0". When transmission is restarted after data is written into TD0BUF,
UART0SR<TBSY> is set to "1". At this time, an INTTXD0 interrupt request is generated.
mission is started, UART0SR<TBFL> is cleared to "0". At this time, an INTTXD0 interrupt request is generated.
Figure 16-16 Transmit Busy Flag and Occurrence of Transmit Buffer Full
If transmission is completed with no waiting data in TD0BUF (when UART0SR<TBFL>="0"),
When TD0BUF has no data, or when data in TD0BUF is transferred to the transmit shift register and trans-
Writing data into TD0BUF sets UART0SR<TBFL> to "1".
Transmit Buffer Full
Transmit busy flag
Writing of
Writing of
data A
data A
Figure 16-17 Occurrence of Transmit Buffer Full
Start Bit0
Start Bit0
Writing of
data B
Bit1
Bit1
Bit2
Bit2
Bit3
Data A
Bit3
Data A
Bit4
Bit4
Page 241
Bit5
Bit5
Bit6
Bit6
Bit7 Stop
Bit7 Stop Start Bit0
Writing of
data B
Bit1
Start Bit0
Bit2
Bit3
Data B
Bit1
Data B
Bit6
Bit6
Bit7 Stop
TMP89FS60
Bit7 Stop