TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 51

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RB000
Quarter of the low-frequency clock
Figure 2-12 Switching of the Main System Clock (fm) (Switching from fcgck to fs/4)
PINTWUC:
SYSCR2<SYSCK>
Example 1: Switching from the NORMAL2 mode to the SLOW1 mode (when fc is used as the basic clock for the high-
Example 2: Switching to the SLOW1 mode after the stable oscillation of the low-frequency clock oscillation circuit is confirmed
Gear clock (fcgck)
Main system clock
(fs/4)
SET
NOP
NOP
CLR
; #### Initialize routine ####
SET
¦
¦
LD
LD
SET
SET
¦
; #### Interrupt service routine of warm-up counter interrupts ####
SET
NOP
NOP
CLR
RETI
¦
frequency clock)
at the warm-up counter (fs=32.768kHz, warm-up time = about 100 ms)
(SYSCR2).4
(SYSCR2).6
(P0FC).2
(WUCCR), 0x02
(WUCDR), 0x33
(EIRL).4
(SYSCR2).5
(SYSCR2).4
(SYSCR2).6
When the rising edge of fcgck is
detected twice after SYSCR2<SYSCK>
is changed from 0 to 1, f is stopped
for synchronization.
Page 35
10/fs (max.)
;SYSCR2<SYSCK> = 1
;(Switches the main system clock to the basic clock for the
;low-frequency clock for the SLOW2 mode)
;Waits for 2 machine cycles
;SYSCR2<XEN> = 0
;(Turns off the high-frequency clock oscillation circuit)
;P0FC2 = 1 (Uses P02/03 as oscillators)
;WUCCR<WUCDIV> = 00 (No division)
;WUCCR<WUCSEL> = 1 (Selects fs as the source clock)
;Sets the warm-up time
;(Determines the time depending on the oscillator characteristics)
;100 ms/1.95 ms = 51.2 → round up to 0x33
;Enables INTWUC interrupts
;SYSCR2<XTEN> = 1
;(Starts the low-frequency clock oscillation and starts the warm-up
;counter)
;SYSCR2<SYSCK> = 1
;(Switches the main system clock to the low-frequency clock)
;Waits for 2 machine cycles
;SYSCR2<XEN> = 0
;(Turns off the high-frequency clock oscillation circuit)
When the rising edge of fs/4 is detected
twice after fm is stopped, fm is switched to fs.
TMP89FS60