TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 203

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA005
14.4.3.2
PWM0 pin output
(TFF0=“1”)
PWM0 pin output
(TFF0=“0”)
INTTC00 interrupt
request
level as the initial state of the PWM0 pin. Setting T00MOD<TFF0> to "1" selects the "H" level as the initial
state of the PWM0 pin. If the PWM0 pin is set as the function output pin in the port setting while the timer
is stopped, the value of T00MOD<TFF0> is output to the PWM0 pin. Table 14-6 shows the list of output
levels of the PWM0 pin.
can be output to PWM0 pin. By using this function, the remote-control waveform can be created eaily.
When a match between the lower 7 bits of the up counter value and the value set to T00PWM<PWMDUTY>
is detected, the output of the PWM0 pin is reversed. When T00MOD<TFF0> is "0", the PWM0 pin changes
from the "L" to "H" level. When T00MOD<TFF0> is "1", the PWM0 pin changes from the "H" to "L" level.
at the 2 × n-th match detection (n=1, 2, 3...). In other words, the PWM0 pin output is reversed at the timing
of T00PWM<PWMDUTY>+1. When T00MOD<TFF0> is "0", the period of the "L" level becomes longer
than the value set to T00<PWMDUTY> by 1 source clock. When T00MOD<TFF0> is "1", the period of the
"H" level becomes longer than the value set to T00PWM<PWMDUTY> by 1 source clock. This function
allows two cycles of output pulses to be handled with a resolution nearly equivalent to 8 bits.
occurs and the up counter is cleared to "0x00". At the same time, the output of the PWM0 pin is reversed.
When T00MOD<TFF0> is "0", the PWM0 pin changes from the "H" to "L" level. When T00MOD<TFF0>
Set the initial state of the PWM0 pin at T00MOD<TFF0>. Setting T00MOD<TFF0> to "0" selects the "L"
And by setting "1" to T001CR<OUTAND> bit, a logical product (AND) pulse of TC00 and TC01’s output
Setting T001CR<T00RUN> to "1" allows the up counter to increment based on the selected source clock.
If T00PWM<PWMAD> is "1", an additional pulse that corresponds to 1 count of the source clock is added
No additional pulse is inserted when T00PWM<PWMAD> is "0".
Subsequently, the up counter continues counting up. When the up counter value reaches 128, an overflow
Operations
Timer start
Table 14-6 List of Output Levels of PWM0 Pin
(Duty pulse
T00PWM
width)
(cycle width)
128 counts
TFF0
Cycle 1
0
1
(Duty pulse
Before the start of
Figure 14-5 PWM0 Pulse Output
T00PWM
width)
(initial state)
(cycle width)
128 counts
operation
Cycle 2
H
L
Additional
pulse
(after the addition-
<PWMDUTY>
Page 187
Cycle 3
T00PWM
matched
al pulse)
PWM0 pin output level
H
L
Cycle 4
Overflow
Additional
H
L
pulse
Cycle 5
Operation stop-
(initial state)
ped
H
L
Cycle 6
Additional
TMP89FS60
pulse