TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 36

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

2.3
System clock controller
RB000
2.3.4
Clock for high-frequency clock
Clock for low-frequency clock
and it consists of a source clock selection circuit, a 3-stage frequency division circuit and a 14-stage counter.
becomes stable and secure the time after the STOP mode is released or the operation mode is changed before the
oscillation by the oscillation circuit becomes stable.
Warm-up counter
The warm-up counter is a circuit that counts the high-frequency clock (fc) and the low-frequency clock (fs),
The warm-up counter is used to secure the time after a power-on reset is released before the supply voltage
oscillation circuit (fc)
oscillation circuit (fs)
2. Prescaler and divider
3. Machine cycle
clock is switched. If the currently operating oscillation circuit is stopped before the main system
clock is switched, the internal condition becomes as shown in Table 2-1 and a system clock
reset occurs. For details of clock switching, refer to "2.3.6 Operation Mode Control".
base timer and other peripheral circuits.
of the divider becomes the output of stage 8 of the divider.
divider becomes fs/4. When SYSCR2<SYSCK> is "1", the outputs of stages 1 to 8 of the
divider and prescaler are stopped.
that follows the release of STOP mode.
corresponds to one main system clock.
ranging from 1-cycle instructions, which require one machine cycle for execution, to 10-cycle
instructions, which require 10 machine cycles for execution, and 13-cycle instructions, which
require 13 machine cycles for execution.
It takes a certain period of time after SYSCR2<SYSCK> is changed before the main system
These circuits divide fcgck. The divided clocks are supplied to the timer counter, the time
When both SYSCR1<DV9CK> and SYSCR2<SYSCK> are "0", the input clock to stage 9
When SYSCR1<DV9CK> or SYSCR2<SYSCK> is "1", the input clock to stage 9 of the
The prescaler and divider are cleared to "0" at a reset and at the end of the warm-up operation
Instruction execution is synchronized with the main system clock (fm).
The minimum instruction execution unit is called a "machine cycle". One machine cycle
There are a total of 11 different types of instructions for the TLCS-870/C1 Series: 10 types
A
B
S
Z
Figure 2-6 Warm-up Counter Circuit
1 2 3
WUCSEL WUCDIV
WUCCR
Page 20
D
C
B
A
S
Z
Enable/disable counting up
WUCRST
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Warm-up counter
XEN XTEN
controller
0 1 2 3 4 5 6 7
SYSCR2
WUCDR
Com-
parator
STOP
Enable CPU operation
TMP89FS60
SYSCR1
INTWUC interrupt