TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 89

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA000
5. Watchdog Timer (WDT)
5.1
fcgck/2
fcgck/2
fcgck/2
fcgck/2
CPU/peripheral
circuits reset
noises or the deadlock conditions, and return the CPU to a system recovery routine.
signals or watchdog timer reset signals.
Configuration
The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious
The watchdog timer signals used for detecting malfunctions can be programmed as watchdog interrupt request
Note:Care must be taken in system designing since the watchdog timer may not fulfill its functions due to disturbing
10
12
14
16
or fs/2
or fs/2
or fs/2
or fs/2
noise and other effects.
3
5
7
9
2
control circuit
Source clock
Disable
Figure 5-1 Watchdog Timer Configuration
Clear
8
WDCNT
Clear time control circuit
2 3 4
8-bit up counter
Disable code
(0xB1)
Control code
decoder
5
WDCDR
Page 73
6 7 8
Clear code
(0x4E)
Overflow
WDCTR
Interrupt
request/reset
signal control
circuit
WDST
Watchdog timer interrupt requestl
Watchdog timer reset signal
TMP89FS60