TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 72

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

3.5
Interrupt Sequence
RA003
Example :SP setting
3.5
3.5.1
3.5.2
“0” by resetting or an instruction. Interrupt acceptance sequence requires 8-machine cycles after the completion of
the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI]
(for maskable interrupts) or [RETN] (for non-maskable interrupts).
Interrupt Sequence
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to
at the start address of a stack. The SP is post-decremented when a subroutine call or a push instruction is executed
or when an interrupt request is accepted. It is pre-incremented when a return or pop instruction is executed.
Therefore, the stack becomes deeper toward lower stack location addresses. Be sure to reserve a stack area having
an appropriate size based on the SP setting.
interrupt master enable flag (IMF) is “0”.
service program
Initial Setting
Interrupt acceptance processing
Using an interrupt requires specifying an SP (stack pointer) for it in advance. The SP is a 16-bit register pointing
The SP is initialized to 00FFH after a reset. If you need to change the SP, do so right after a reset or when the
Interrupt acceptance processing is packaged as follows.
Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt
Note:When the contents of PSW are saved on the stack, the contents of register bank and IMF are also saved.
1. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any
2. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
3. The contents of the program counter (PC) and the program status word, including the interrupt master
4. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector
5. The instruction stored at the entry address of the interrupt service program is executed.
following interrupt.
enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile,
the stack pointer (SP) is decremented by 3.
table, is transferred to the program counter.
LD
LD
ADD
Figure 3-2 Vector table address and Entry address
0xFFF4
0xFFF5
Vector table address
SP, 023FH
SP, SP+04H
SP, 0010H
0xD2
0x03
; SP = 023FH
; SP = SP + 04H
; SP = SP + 0010H
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0xD203
0xD204
Vector table address
0x0F
0x06
TMP89FS60