TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 108

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA007
should be externally held until the input data is read from outside or reading should be performed several times before
processing. Figure 8-1 shows input/output timing examples.
be recognized from outside, so that transient input such as chattering must be processed by the program. Data is output
to an I/O port in the next cycle of the write cycle during execution of the write instruction.
Each output port contains a latch, which holds the output data. No input port has a latch, so the external input data
External data is read from an I/O port in the read cycle during execution of the read instruction. This timing cannot
Note:The positions of the read and write cycles may vary, depending on the instruction.
Internal read
signal
Data input
Internal write
signal
Data output
System clock
Instruction
execution cycle
System clock
Instruction
execution cycle
Figure 8-1 Input/Output Timing (Example)
Fetch cycle
Fetch cycle
Example: LD A, (x)
Example: LD (x), A
Fetch cycle
Fetch cycle
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(a) Input timing
(b) Output timing
Read cycle
Write cycle
TMP89FS60