TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 91

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA000
8-bit up counter monitor
Watchdog timer status
(0x0FD6)
(0x0FD7)
WDCNT
WDST
Note:WDCDR is a write-only register and must not be accessed by using a read-modify-write instruction, such as a
Note 1: WDST<WINTST2> and WDST<WINTST1> are cleared to "0" by reading WDST.
Note 2: Values after reset are read from bits 7 to 3 of WDST.
bit operation.
WINTST2
WINTST1
WDCNT
WDTST
Read/Write
Read/Write
Bit Symbol
Bit Symbol
After reset
After reset
Monitors the count value of the 8-bit
up counter
Watchdog timer interrupt request
signal factor status 2
Watchdog timer interrupt request
signal factor status 1
Watchdog timer operating state sta-
tus
R
7
0
7
0
-
R
6
0
6
1
-
R
5
0
The count value of the 8-bit up counter is read.
5
0
-
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0 :
1 :
0 :
1 :
0 :
1 :
No watchdog timer interrupt request signal has occurred.
A watchdog timer interrupt request signal has occurred due to the overflow
of the 8-bit up counter.
No watchdog timer interrupt request signal has occurred.
A watchdog timer interrupt request signal has occurred due to releasing of
the 8-bit up counter outside the clear time.
Operation disabled
Operation enabled
R
4
0
4
1
-
WDCNT
R
R
1
3
0
3
-
WINTST2
R
2
0
2
0
WINTST1
R
1
0
1
0
TMP89FS60
WDTST
R
0
0
0
1