TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 69

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA003
Interrupt enable register (EIRL)
Interrupt enable register (EIRH)
Interrupt enable register (EIRE)
Interrupt enable register (EIRD)
(0x003C)
(0x003D)
(0x003A)
(0x003B)
EIRH
EIRD
EIRL
EIRE
Note 1: Do not set the IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time.
Note 2: In the main program, before manipulating the interrupt enable flag (EF), be sure to clear the master enable flag (IMF) to
Note 3: When a read instruction is executed on EIRL, bits 3 to 1 are read as "0". Other unused bits are read as "0".
Read/Write
Read/Write
Read/Write
Read/Write
EF27 to
Bit Symbol
Bit Symbol
Bit Symbol
Bit Symbol
After reset
After reset
After reset
After reset
"0" (Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the EF (Enable interrupt by EI
instruction)
In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. However, if
using multiple interrupt in the interrupt service routine, manipulate the EF before setting the IMF to "1".
Function
Function
Function
Function
EF4
IMF
Individual interrupt enable flag
(Specified for each bit)
Interrupt master enable flag
INTSBI0/IN-
INTTXD0
INTTXD1
TSIO0
EF15
EF23
R/W
R/W
R/W
EF7
R
7
0
7
0
7
0
7
0
-
INTRXD0 /
INTRXD1/
INTTCA0
INTSIO0
INTSIO1
EF14
EF22
EF6
R/W
R/W
R/W
R
6
0
6
0
6
0
6
0
-
INTTC01
INTTCA1
INTTBT
EF13
EF21
R/W
R/W
R/W
EF5
R
5
0
5
0
5
0
5
0
-
Page 53
0:
1:
0:
1:
Disables the acceptance of each maskable interrupt.
Enables the acceptance of each maskable interrupt.
Disables the acceptance of all maskable interrupts.
Enables the acceptance of all maskable interrupts.
INTWUC
INTTC00
EF12
EF20
INT4
EF4
R/W
R/W
R/W
R
4
0
4
0
4
0
4
0
-
INTTXD2
INTRTC
EF11
EF19
EF27
INT3
R/W
R/W
R/W
R
3
0
3
0
3
0
3
0
-
INTRXD2
INTADC
EF10
EF18
EF26
INT2
R/W
R/W
R/W
R
2
0
2
0
2
0
2
0
-
INTVLTD
INTTC03
EF17
EF25
INT1
EF9
R/W
R/W
R/W
R
1
0
1
0
1
0
1
0
-
TMP89FS60
master ena-
INTTC02
Interrupt
ble flag
EF16
EF24
INT5
INT0
R/W
R/W
R/W
R/W
IMF
EF8
0
0
0
0
0
0
0
0