TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 309

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA002
Example :Generate the stop condition
18.5.5
CHK_BB:
transferring data. The following explains how to restart the serial bus interface circuit.
SDA0 pin retains the high level and the SCL0 pin is released.
released.
low level by other devices.
condition and slave address generation".
mode I
to confirm that a bus is free until the time to generate a start condition.
SCL0 pin
SCL (Bus)
SDA0 pin
SBI0CR2<PIN>
SBI0SR2<BB>
Restart is used to change the direction of data transfer between a master device and a slave device during
Clear SBI0CR2<MST>, SBI0CR2<TRX> and SBI0CR2<BB> to "0" and set SBI0CR2 <PIN> to "1". The
Since this is not a stop condition, the bus is assumed to be in a busy state from other devices.
Check SBI0SR2<BB> until it becomes "0" to check that the SCL0 pin of the serial bus interface circuit is
Check SBI0SR2<LRB> until it becomes "1" to check that the SCL line on the bus is not pulled down to the
After confirming that the bus stays in a free state, generate a start condition in the procedure "18.5.2 Start
In order to meet the setup time at a restart, take at least 4.7μs of waiting time by the software in the standard
Restart
Note:When the master is in the receiver mode, it is necessary to stop the data transmission from the slave
2
C bus standard or at least 0.6μs of waiting time in the fast mode I
SBI0CR2<MST>="1"
SBI0CR2<TRX>="1"
SBI0CR2<BB>="0"
SBI0CR2<PIN>="1"
device before the STOP condition is generated. To stop the transmission, the master device make the
slave device receiving a negative acknowledge. Therefore, SBI0SR2<LRB> is "1" before generating the
Restart and it can not be confirmed that SCL line is not pulled down by other devices. Please confirm
the SCL line state by reading the port.
LD
TEST
JR
Figure 18-21 Stop Condition Generation
(SBI0CR2), 0xD8
(SBI0SR2).BB
T, CHK_BB
; Sets SBI0CR2<MST>, <TRX> and <PIN> to "1" and SBI0CR2<BB> to "0"
;Waits until the bus is set free
Page 293
If the SCL of the bus is pulled
down by other devices, the stop
condition is generated after it is
released
2
C bus standard from the time of restarting
Stop condition
TMP89FS60