TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 256

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TMP89xy60UG/FG

Manufacturer Part Number
TMP89xy60UG/FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP89xy60UG/FG

Package
LQFP64/QFP64
Rom Types (m=mask,p=otp,f=flash)
M/F
Rom Size
32/60
Ram Size
3K
Driver Led
8
Driver Lcd
-
Spi/sio Channels
-
Uart/sio Channels
2
I2c/sio Channels
1
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
16
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
2
Timer Counter 8-bit Channel
4
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
Y
Number Of I/o Ports
58
Power Supply (v)
4.3 to 5.5
16.12
Status Flag
RA001
16.12.4
RXD0 pin input
UART0SR<RBFL>
INTRXD0 interrupt request
Reading of UART0SR
Reading of RD0BUF
RD0BUF
RD0BUF is read subsequently.
when RD0BUF is read subsequently. In this case, UART0SR<RBFL> will be cleared to "0" when UART0SR is
read again and RD0BUF is read.
Loading the received data in RD0BUF sets UART0SR<RBFL> to "1".
If UART0SR<RBFL> is "1" when UART0SR is read, UART0SR<RBFL> will be cleared to "0" when
If UART0SR<RBFL> is set to "1" after UART0SR is read, UART0SR<RBFL> will not be cleared to "0"
Receive Data Buffer Full
Figure 16-15 Occurrence of Receive Data Buffer Full
Start Bit1
Bit0
Data A
Bit7 Stop Start Bit0
Data A
Page 240
Reading of data A
Bit1
Data B
Bit7 Stop
Data B
Reading of data B
RBFL is cleared to “0” when
RD0BUF is read after
reading RBFL=“1”.
TMP89FS60

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