TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 301

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA002
SCL (Bus)
SDA pin (Master 1)
SDA pin (Master 2)
SDA (Bus)
lost". A master device which loses arbitration releases the SDA pin and the SCL pin in order not to effect data
transmitted from other masters with arbitration. When more than one master sends the same data at the first word,
arbitration occurs continuously after the second word.
the SCL line. If the levels are unmatched, arbitration is lost and SBI0SR2<AL> is set to "1".
is switched to a slave receiver mode. Thus, the serial bus interface circuit stops output of clock pulses during data
transfer after the SBI0SR2<AL> is set to "1". After the data transfer is completed, SBICR2<PIN> is cleared to
"0" and the SCL pin is pulled down to the low level.
data to the SBI0CR2.
SBI0SR2<AL>
SBI0CR2<MST>
SBI0CR2<TRX>
SBI0CR2<PIN>
Access to SBI0DBR
or SBI0CR2
INTSBI0 Interrupt request
Master A
Master B
The serial bus interface circuit compares levels of a SDA line of a bus with its SDA pin at the rising edge of
When SBI0SR2<AL> is set to "1", SBI0CR2<MST> and SBI0CR2<TRX> are cleared to "0" and the mode
SBI0SR2<AL> is cleared to "0" by writing data to the SBI0DBR, reading data from the SBI0DBR or writing
Figure 18-13 Example When Master B is a Serial Bus Interface Circuit
SCL pin
SDA pin
SCL pin
SDA pin
D7A
D7A
1
1
D6A
D6A
Figure 18-12 Arbitration Lost
2
2
D5A
3
3
Releasing SDA pin and SCL pin
to high level as losing arbitration.
D4A
Stop clock output
4
4
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D3A D2A D1A D0A
5
5
a
6
6
b
7
7
The SDA pin becomes "1" after losing arbitration.
8
8
9
9
D7A’
1
D6A’
2
TMP89FS60
D5A’
3