TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 8
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TMP89xy60UG/FG
Manufacturer Part Number
TMP89xy60UG/FG
Description
Manufacturer
Toshiba
Datasheet
1.TMP89XY60UGFG.pdf
(432 pages)
Specifications of TMP89xy60UG/FG
Package
LQFP64/QFP64
Rom Types (m=mask,p=otp,f=flash)
M/F
Rom Size
32/60
Ram Size
3K
Driver Led
8
Driver Lcd
-
Spi/sio Channels
-
Uart/sio Channels
2
I2c/sio Channels
1
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
16
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
2
Timer Counter 8-bit Channel
4
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
Y
Number Of I/o Ports
58
Power Supply (v)
4.3 to 5.5
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3. Interrupt Control Circuit
4. External Interrupt control circuit
5. Watchdog Timer (WDT)
ii
2.5 Revision History......................................................................................................................46
3.1 Configuration...........................................................................................................................49
3.2 Interrupt Latches (IL27 to IL3)................................................................................................50
3.3 Interrupt Enable Register (EIR)...............................................................................................51
3.4 Maskable Interrupt Priority Change Function.........................................................................54
3.5 Interrupt Sequence...................................................................................................................56
3.6 Software Interrupt (INTSW)....................................................................................................60
3.7 Undefined Instruction Interrupt (INTUNDEF).......................................................................60
3.8 Revision History......................................................................................................................61
4.1 Configuration...........................................................................................................................63
4.2 Control.....................................................................................................................................63
4.3 Function...................................................................................................................................67
5.1 Configuration...........................................................................................................................73
5.2 Control.....................................................................................................................................74
5.3 Functions..................................................................................................................................76
3.3.1
3.3.2
3.5.1
3.5.2
3.5.3
3.5.4
3.6.1
3.6.2
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
2.4.4.8
2.4.4.9
3.5.3.1
3.5.3.2
3.5.3.3
4.3.3.1
4.3.3.2
4.3.3.3
4.3.4.1
4.3.4.2
4.3.4.3
Interrupt master enable flag (IMF)....................................................................................................................................51
Individual interrupt enable flags (EF27 to EF4)................................................................................................................51
Initial Setting......................................................................................................................................................................56
Interrupt acceptance processing.........................................................................................................................................56
Saving/restoring general-purpose registers........................................................................................................................57
Interrupt return...................................................................................................................................................................59
Address error detection......................................................................................................................................................60
Debugging..........................................................................................................................................................................60
Low power consumption function.....................................................................................................................................68
External interrupt 0............................................................................................................................................................68
External interrupts 1/2/3....................................................................................................................................................69
External interrupt 4............................................................................................................................................................70
External interrupt 5............................................................................................................................................................72
Setting of enabling/disabling the watchdog timer operation.............................................................................................76
Setting the clear time of the 8-bit up counter.....................................................................................................................76
Setting the overflow time of the 8-bit up counter..............................................................................................................77
Setting an overflow detection signal of the 8-bit up counter.............................................................................................77
Writing the watchdog timer control codes.........................................................................................................................78
Reading the 8-bit up counter..............................................................................................................................................78
Reading the watchdog timer status....................................................................................................................................78
Internal factor reset detection status register
How to use the external reset input pin as a port
Using PUSH and POP instructions
Using data transfer instructions
Using a register bank to save/restore general-purpose registers
Interrupt request signal generating condition detection function
A noise canceller pass signal monitoring function when interrupt request signals are generated
Noise cancel time selection function
Interrupt request signal generating condition detection function
A noise canceller pass signal monitoring function when interrupt request signals are generated
Noise cancel time selection function
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