TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 55

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RB000
System control register 4
System control status register 4
(0x0FDF)
(0x0FDF)
SYSCR4
SYSSR4
Note 3: After SYSCR3<RSTDIS> is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3<RSTDIS>) in NOR-
Note 4: Bits 7 to 3 of SYSCR3 are read as "0".
Note 1: SYSCR4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit oper-
Note 2: In the case of 89FS60, if setting "1" to IRSTSR<FCLR>, each flag of IRSTSR register is cleared to "0" without setting
Note 3: After SYSCR3<RSTDIS> is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3<RSTDIS>) in NORMAL
Note 4: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR<FCLR> in NORMAL mode
Note 1: The enabled SYSCR3<RSTDIS> is initialized by a power-on reset only, and cannot be initialized by any other reset signals.
Note 2: Bits 7 to 3 of SYSCR4 are read as "0".
RSTDISS
SYSCR4
Read/Write
Read/Write
Bit Symbol
Bit Symbol
MAL1 mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> may be enabled at unexpec-
ted timing.
After reset
ation.
"0x71" to SYSCR4. Nevertheless, in order to keep software compatibility with other product, it is recommended to describe
the program code that set "0x71" to IRSTSR<FCLR> after setting "1" to IRSTSR<FCLR>.
mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> may be enabled at unexpected tim-
ing.
when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> may be enabled at unexpected timing.
After reset
The value written in SYSCR3 is reset by a power-on reset and other reset signals.
Writes the SYSCR3 data control
code.
External reset input enable status
R
7
0
7
0
-
R
6
0
6
0
-
R
5
0
5
0
-
Others :
Page 39
0xD4 :
0xB2 :
0x71 :
0 :
1 :
Enables the contents of SYSCR3<RSTDIS>
Enables the contents of SYSCR3<RAREA> and SYSCR3 <RVCTR>
Enables the contents of IRSTSR<FCLR> *Note2
Invalid
The enabled SYSCR3<RSTDIS> data is "0".
The enabled SYSCR3<RSTDIS> data is "1".
R
4
0
4
0
-
SYSCR4
W
R
0
3
0
3
-
(RVCTRS)
R
2
0
2
0
(RAREAS)
R
1
0
1
0
TMP89FS60
RSTDISS
R
0
0
0
0