TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 35

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RB000
2.3.3.3
A quarter of the basic clock
for the low-frequency clock
SYSCR2<SYSCK>
SYSCR1<DV9CK>
changed.
frequency clock (fc).
peripheral circuits, from the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs).
The timing generator has the following functions:
Gear clock fcgck
(1)
The gear clock (fcgck) may be longer than the set clock width, immediately after CGCR<FCGCKSEL> is
Immediately after reset release, the gear clock (fcgck) becomes the clock that is a quarter of the high-
The timing generator is a circuit that generates system clocks to be supplied to the CPU core and the
Timing generator
Note:Don't change CGCR<FCGCKSEL> in the SLOW mode. This may stop the gear clock (fcgck) from being
a machine cycle counter.
1. Generation of the main system clock (fm)
2. Generation of clocks for the timer counter, the time base timer and other peripheral circuits
changed.
The timing generator consists of a main system clock generator, a prescaler, a 21-stage divider and
Configuration of timing generator
1. Main system clock generator
clock (fs) for the main system clock (fm) to operate the CPU core.
the clock that is a quarter of the low-frequency clock (fs).
Figure 2-5 Configuration of Timing Generator
This circuit selects the gear clock (fcgck) or the clock that is a quarter of the low-frequency
Clearing SYSCR2<SYSCK> to "0" selects the gear clock (fcgck). Setting it to "1" selects
Table 2-2 Gear Clock (fcgck)
Prescaler
CGCR<FCGCKSEL>
00
01
10
11
Divider
Timer counter, time base timer and other peripheral circuits
Main system clock generator
Page 19
Multiplexer
Reserved
A
B
fcgck
S
fc / 4
fc / 2
fc
Y
Main system clock
fm
Divider
Machine cycle counter
TMP89FS60