TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 221

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA005
T001CR<T01RUN>
T01MOD<TFF1>
Source clock
Counter
Write to T00PWM
Write to T01PWM
Double buffer
PWMAD3 to 0
PWMDUTY
PWM1 pin output
INTTC00 interrupt request
INTTC01 interrupt request
(Example) Operate TC00 and TC01 in the 12-bit PWM mode with the operation clock of fcgck/2 and output a duty pulse
Write m (0001)
Becomes the level selected at
TFF1 while the timer is stopped
Write k
nearly equivalent to 14.0625 μs in 64μs cycles (fcgck = 8 MHz)
(Actually, output a duty pulse of 225 μs in total in 16 cycles (1024 μs))
km
km (0001)
0001
Figure 14-15 12-bit PWM Mode Timing Chart
Timer start
(Duty pulse)
SET
SET
LD
DI
SET
EI
LD
LD
LD
LD
0
km
1
256 counts
(Cycle 1)
When the double buffer is enabled (T01MOD<DBE1>=”1”)
Match detection
km
(P7FC).1
(P7CR).1
(POFFCR0),0x10
(EIRH).4
(T01MOD),0xF2
(T00PWM),0x84
(T01PWM),0x03
(T001CR),0x06
km
+1
(Duty pulse)
256
Overflow
Counter
clear
Interrupt request
0
km
256 counts
1
(Cycle 2)
Page 205
Match detection
km
km
+1
; Sets P7FC1 to "1"
; Sets P7CR1 to "1"
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
; Selects the 12-bit PWM mode and fcgck/2
; Sets the timer register (duty pulse)
; (14.0625μs × 16) / (2/fcgck) = 0x384
; Sets the timer register (duty pulse)
; Starts TC00 and TC01
256
Overflow
(Duty pulse)
Counter
clear
Interrupt request
0
km+1
1
256 counts
Additional pulse
(Cycle 9)
Match detection
km
km
+1
(Duty pulse)
Overflow
256
Interrupt request
Counter
clear
0
km
256 counts
(Cycle 16)
1
Write s (0011)
Write r
rs (0011)
Match detection
km
km
+1
(Duty pulse)
TMP89FS60
256
rs
Counter
clear
0011
Interrupt request
0
(Cycle 17)
rs
1
rs